• 한국정밀공학회지
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• 제18권5호
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• pp.147-156
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• 2001

본 연구에서는 칩 캡슐화 성형 공정 중의 패들 변형을 해석하기 위한 방법론이 연구되었다. 헬레쇼오 근사 모델에 근거한 유한요소법이 칩 캐비티에서의 유동 해석을 위해 사용되었다. 리드 프레임 상의 구멍을 통한 통과 유동해석을 위한 근사모델이 제안되었다. 본 연구에서 제시된 해석모델에 의해 계산된 값과 실험 값은 잘 일치하였다. 유동해석을 통하여 리드프레임과 패들에 의해 경계를 이루고 있는 상, 하 캐비티간의 압력차가 계산되었다. 최종적으로 패들 변형이 압력차 계산 값을 이용하여 계산되게 된다.

• 한국정밀공학회지
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• 제13권12호
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• pp.13-21
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• 1996

In this paper, methods to reduce wire sweep during the chip-encapsulation process have been studide. Two methods have been tried for this purpose, namely runner balancing and ram velocity control. Runner balancing has been achieved automatically by using a computer program. Ram-velocity control has been achieved using empirical rules and results from a flow simulation of the encapsulation process. A mold which has 12 cavities for chip has been used as a case study. The simulation results show that the wire sweep obtained from the optimal process condition is about 1/5 of that from initial, unoptimized condition.

• 한국정밀공학회지
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• 제15권2호
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• pp.99-106
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• 1998

In this paper, we have constructed an expert system for semiconductor chip encapsulation which combines a knowledge-based system with CAE software. The knowledge-base module includes heuristic and pre analysis knowledge for evaluation and redesign. Evaluation of the initial design and generation of redesign recommendations can be developed from the rules as applied to a given chip package. The CAE programs can be used for simulating the filling and packing stage of encapsulation process. The expert system is a new tool which enables package design or process conditions with high yields and high productivity.

• 한국정밀공학회지
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• 제12권12호
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• pp.91-99
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• 1995

An effort has been made to more accurately analyze the flow in the chip cavity, particularly to model the flow through the openings in the leadframe and correctly treat the thermal boundary condition at the leadframe. The theoretical analysis of the flow has been done by using the Hele- Shaw approximation in each cavity separated by a leadframe. The cross-flow through the openings in the leadframe has been incorporated into the Hele-Shaw formulation as a mass source term. The temperature of the leadframe has been calculated based on energy balance in the leadframe. The flow behavior in the leadframe has been verified experimentally. In the experiment, a transparent mold and clear fluid have been used for flow visualization. Comparisons were made between the calculation and experimental results which showed a good agreement.

• 한국정밀공학회지
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• 제18권2호
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• pp.102-110
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• 2001

In this paper, methods to analyze wire sweep and paddle shift during the semiconductor ship-encapsulation process have been studied. The analysis of wire sweep includes flow-field analysis in a complicated geometry, drag-force calculation for given flow of fluid, and wire-deformation calculation for given loads. The paddle-shift analysis is used to analyze the deformation of the paddle due to the pressure difference in two cavities. the analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The numerical solution is used for more accurate calculation of wire-sweep. The numerical results of wire sweep show good agreements with the experimental ones.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1995년도 춘계학술대회 논문집
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• pp.477-480
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• 1995

Dccisions of optimal filling conditions for the chip encapsulation have been done primarily by an ad hoc use of expertise accumulated over the years because the chip encapsulation process is quite complicated. The current CAE systems do not provide mold designers with necessary knowledge of the chip encapsulation for the successful design of optimal filling except flow simulation capability. There have been no attempts to solve the optimal filling problem in the process of the chip encapsulation. In this paper, we have constructed an design system for optimal filling to avoid short shot in the chip encapsulation process which combines an optimization methodology with CAE software.