Reduction of Wire Sweep during Chip Encapsulation by Runner Balancing and Ram Control

반도체 칩 캡슐화 공정에 있어서 와이어 스윕(wire sweep) 최소화에 관한 연구

In this paper, methods to reduce wire sweep during the chip-encapsulation process have been studide. Two methods have been tried for this purpose, namely runner balancing and ram velocity control. Runner balancing has been achieved automatically by using a computer program. Ram-velocity control has been achieved using empirical rules and results from a flow simulation of the encapsulation process. A mold which has 12 cavities for chip has been used as a case study. The simulation results show that the wire sweep obtained from the optimal process condition is about 1/5 of that from initial, unoptimized condition.