한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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- Pages.94-94
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- 2008
SiGe-Si-SiGe 채널구조를 이용한 JFET 시뮬레이션
Simulation of Junction Field Effect Transistor using SiGe-Si-SiGe Channel Structure
- 박병관 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
- 양하용 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
- 김택성 (전북대학교 반도체.화학공학부 반도체 물성연구소) ;
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심규환
(전북대학교 반도체.화학공학부 반도체 물성연구소)
- Park, B.G. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
- Yang, H.Y. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
- Kim, T.S. (Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University) ;
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Shim, K.H.
(Semiconductor Physics Research Center, Department of Semiconductor Science and Technology, and Department of Physics, Chonbuk National University)
- 발행 : 2008.11.06
초록
We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and