• Journal of Computing Science and Engineering
• /
• v.7 no.1
• /
• pp.53-66
• /
• 2013

Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.6 s.44
• /
• pp.113-123
• /
• 2006

Flash memory has been increasingly used in handhold devices not only for data storage, but also for code storage. Because NAND flash memory only provides sequential access feature, a traditionally accepted solution to execute the program from NAND flash memory is shadowing. But, shadowing has significant drawbacks increasing a booting time of the system and consuming severe DRAM space. Demand paging has obtained significant attention for program execution from NAND flash memory. But. one of the issues is that there has been no effort to bound demand paging cost in flash memory and to analyze the worst case performance of demand paging. For the worst case timing analysis of programs running from NAND flash memory. the worst case demand paging costs should be estimated. In this paper, we propose two different WCRT analysis methods considering demand paging costs, DP-Pessimistic and DP-Accurate, depending on the accuracy and the complexity of analysis. Also, we compare the accuracy butween DP-Pessimistic and DP-Accurate by using the simulation.

• The Transactions of the Korea Information Processing Society
• /
• v.6 no.11
• /
• pp.3131-3139
• /
• 1999

Satisfying the rigid timing requirements of various real-time activities in real-time systems often requires some special methods to tune the systems run-time behaviors. Unbounded blocking can be caused when a high priority activity cannot preempt a low priority activity. In such situation, it is said that a priority inversion has occurred. The priority inversion is one of the problems which may prevent threads from meeting the deadlines in the real-time systems. It is difficult to remove such priority inversion problems in the kernel at the same time to bound the worst case blocking time for the threads. A thread is a piece of executable code which has access to data and stack. In this paper, a new real-time systems. It is difficult to remove such priority inversion problems in the kernel at the same time to bound the worst case blocking time for the threads. A threads is a piece of executable code which has access to data and stack. In this paper, a new real-time server model, which minimizes the duration of priority inversion, is proposed to reduce the priority inversion problem. The proposed server model provides a framework for building a better server structure, which can not only minimize the duration of the priority inversion, but also reduce the deadline miss ratio of higher priority threads.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.5B
• /
• pp.257-269
• /
• 2007

This paper proposes a novel method to perform a quantitative analysis of message complexity and applies this method in comparing the message complexity among the mobile ad hoc network (MANET) address autoconfiguration protocols (AAPs). To obtain the upper bound of the message complexity of the protocols, the O-notation of a MANET group of N nodes has been applied. The message complexity of the single node joining case in Strong DAD, Weak DAD with proactive routing protocols (WDP), Weak DAD with on-demand routing protocols (WDO), and MANETconf has been derived as n(mO(N)+O(t)), n(O(N)+O(t)), n(O(N)+2O(t)), and nO((t+1)N)+O(N)+O(2) respectively. In order to verify the bounds, analytical simulations that quantify the message complexity of the address autoconfiguration process based on the different coflict probabilities are conducted.

• Journal of Positioning, Navigation, and Timing
• /
• v.12 no.1
• /
• pp.51-58
• /
• 2023

Geofencing supports unmanned aerial vehicle (UAV) operation by defining stay-in and stay-out regions. National Aeronautics and Space Administration (NASA) has developed a prototype of the geofencing function, SAFEGUARD, which prevents stayout region violation by utilizing position estimates. Thus, SAFEGUARD depends on navigation system performance, and the safety risk associated with the navigation system uncertainty should be considered. This study presents a methodology to compute the safety risk assessment-based along-track position error bound under nominal and Global Navigation Satellite Systems (GNSS) failure conditions. A Kalman filter system using pseudorange measurements as well as pseudorange rate measurements is considered for determining the position uncertainty induced by velocity uncertainty. The worst case pseudorange and pseudorange rate fault-based position error bound under the GNSS failure condition are derived by applying a Receiver Autonomous Integrity Monitor (RAIM). Position error bound simulations are also conducted for different GNSS fault hypotheses and constellation conditions with a GNSS/INS integrated navigation system. The results show that the proposed along-track position error bounds depend on satellite geometries caused by UAV attitude change and are reduced to about 40% of those of the single constellation case when using the dual constellation.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.27 no.2
• /
• pp.24-28
• /
• 2004

This paper considers a scheduling problem concerned with an assembly system where two components are first treated In their own parallel machines and then pulled to be assembled into a final product at a single assembly machine. The objective measure is the mean completion time of jobs(a finite number of products). Through characterizing solution properties, we obtain the worst case error bounds of an arbitrary permutation and a SPT based heuristic.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.20 no.4
• /
• pp.455-462
• /
• 2010

We investigate the worst case complexity regarding the number of comparisons for a simple and stable merging algorithm. The complexity analysis shows that the algorithm performs O(mlog(n/m)) comparisons for two sequences of sizes m and n $m{\leq}n$. So, according to the lower bound for merging $\Omega$(mlog(n/m)), the algorithm is asymptotically optimal regarding the number of comparisons. For proving the worst case complexity we divide the domain of all inputs into two disjoint cases. For either of these cases we will extract a special subcase and prove the asymptotic optimality for these two subcases. Using this knowledge for special cases we will prove the optimality for all remaining cases. By using this approach we give a transparent solution for the hardly tractable problem of delivering a clean complexity analysis for the algorithm.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.24 no.4
• /
• pp.708-712
• /
• 1987

This paper deals with minimizing layout area of VLSI design. A long wire in a VLSI layout causes delay which can be reduced by using a driver. There can be significant area increase when many drivers are introduced in a layout. This paper describes a method to obtain tight bound on the worst-case increase in area when drivers are introduced along many long wires in a layout. The area occupied by minimum-area embedding for a circuit can depend on the aspect ratio of the bounding rectangle of the layout. This paper presents a separator-based area optimal embeddings for VLSI graphs in rectangles of several aspect ratios.

• Journal of Communications and Networks
• /
• v.8 no.1
• /
• pp.70-84
• /
• 2006

We propose a new distributed QoS routing scheme called pre-computation based selective probing (PCSP). The PCSP scheme is designed to provide an exact solution to the constrained optimization problem with moderate overhead, considering the practical environment where the state information available for the routing decision is not exact. It does not limit the number of probe messages, instead, employs a qualitative (or conditional) selective probing approach. It considers both the cost and QoS metrics of the least-cost and the best-QoS paths to calculate the end-to-end cost of the found feasible paths and find QoS-satisfying least-cost paths. It defines strict probing condition that excludes not only the non-feasible paths but also the non-optimal paths. It additionally pre-computes the QoS variation taking into account the impreciseness of the state information and applies two modified QoS-satisfying conditions to the selection rules. This strict probing condition and carefully designed probing approaches enable to strictly limit the set of neighbor nodes involved in the probing process, thereby reducing the message overhead without sacrificing the optimal properties. However, the PCSP scheme may suffer from high message overhead due to its conservative search process in the worst case. In order to bound such message overhead, we extend the PCSP algorithm by applying additional quantitative heuristics. Computer simulations reveal that the PCSP scheme reduces message overhead and possesses ideal success ratio with guaranteed optimal search. In addition, the quantitative extensions of the PCSP scheme turn out to bound the worst-case message overhead with slight performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.6A
• /
• pp.577-582
• /
• 2008

In this paper, we present a scheme to overcome the worst case complexity of the sphere decoder. If the number of visited nodes reaches the threshold, the detected symbol vector is determined between two candidate symbol vectors. One candidate symbol vector is obtained from the demodulated output of ZF receiver which is initial stage of the sphere decoder. The other candidate symbol vector consists of two sub-symbol vectors. The first sub-symbol vector consists of lately visited nodes running from the most upper layer. The second one contains corresponding demodulated outputs of ZF receiver. Between these two candidate symbol vectors, the one with smaller euclidean distance to the received symbol vector is chosen as detected symbol vector. In addition, we show the upper bound of symbol error rate performance for the sphere decoder using the proposed scheme. In the simulation, the proposed scheme shows the significant reduction of the worst case complexity while having negligible SER performance degradation.