• MALSORI
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• no.65
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• pp.93-103
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• 2008

In this paper, we propose a method for optimizing a multiple pronunciation dictionary used for modeling pronunciation variations of non-native speech. The proposed method removes some confusable pronunciation variants in the dictionary, resulting in a reduced dictionary size and less decoding time for automatic speech recognition (ASR). To this end, a confusability measure is first defined based on the Levenshtein distance between two different pronunciation variants. Then, the number of phonemes for each pronunciation variant is incorporated into the confusability measure to compensate for ASR errors due to words of a shorter length. We investigate the effect of the proposed method on ASR performance, where Korean is selected as the target language and Korean utterances spoken by Chinese native speakers are considered as non-native speech. It is shown from the experiments that an ASR system using the multiple pronunciation dictionary optimized by the proposed method can provide a relative average word error rate reduction of 6.25%, with 11.67% less ASR decoding time, as compared with that using a multiple pronunciation dictionary without the optimization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.75-80
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• 2009

RSA cryptoprocessors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, a fast 32bit modular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Journal of IKEEE
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• v.20 no.4
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• pp.449-453
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• 2016

Failures would occur because of the hostile nature environment in Wireless Sensor Networks (WSNs) which is deployed randomly. Therefore, considering faults in WSNs is essential when we design WSN. This paper classified fault model in the sensor node. Especially, this paper proposed new error correcting code scheme and fault recovery algorithm in the CH(Cluster Head) node. For the range of the small size information (<16), the parity size of the proposed code scheme has the same parity length compared with the Hamming code, and it has a benefit to generate code word very simple way. This is very essential to maintain reliability in WSN with increase power efficiency.

• Journal of Communications and Networks
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• v.7 no.4
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• pp.450-461
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• 2005

In this paper, we derive analytical expressions for the exact pairwise error probability (PEP) of a space-time coded system operating over spatially correlated fast (constant over the duration of a symbol) and slow (constant over the length of a code word) fad­ing channels using a moment-generating function-based approach. We discuss two analytical techniques that can be used to evaluate the exact-PEPs (and therefore, approximate the average bit error probability (BEP)) in closed form. These analytical expressions are more realistic than previously published PEP expressions as they fully account for antenna spacing, antenna geometries (uniform linear array, uniform grid array, uniform circular array, etc.) and scattering models (uniform, Gaussian, Laplacian, Von-mises, etc.). Inclusion of spatial information in these expressions provides valuable insights into the physical factors determining the performance of a space-time code. Using these new PEP expressions, we investigate the effect of antenna spacing, antenna geometries and azimuth power distribution parameters (angle of arrival/departure and angular spread) on the performance of a four-state QPSK space-time trellis code proposed by Tarokh et al. for two transmit antennas.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.44-48
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• 2008

According to increment of stage, the speed of changeable stage Carry-increment adder can be close to $O(\sqrt{2n})$ because the word length which is computed in stage can be lengthened by 1 bit. But the number of stage bits is increased, fan-out of carry which is inputted in stage is increased. So tile speed can be slow. This paper presents a new carry-increment adder design method to fix the number of fan-outs regardless of the number of stages. By layout simulation of 37-bit adder, the area can be Increased up to 40%, but speed improvement up to 75% can be achieved, by the proposed method, compared with a conventional method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.740-743
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• 2008

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, $32b^*32b$ multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the stalks flag. In this paper, a fast 32bit nodular multiplier which is required to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The proposed architecture prototype of the multiplier unit was automatically synthesized, and successfully operated at the frequency in the target RSA processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2397-2404
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• 2012

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In order to improve the performance, it is necessary to employ an iterative coding scheme. Among the iterative coding scheme, turbo codes and LDPC codes are dominant channel coding schemes in recent. This paper concluded that turbo coding scheme is optimal for underwater communications system in aspect to performance, coded word length, and equalizer combining. Also, decision directed phase recovery was used for correcting phase offset induced by multipath. Based on these algorithms, we confirmed the performance in the environment of oceanic experimentation.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.76-82
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• 2004

A method of designing a state feedback gam achieving a specified insensitivity of the closed-loop trajectory by the singularly perturbed unified system using the operators is proposed. The order of system is reduced by the singular perturbation technique by ignoring the fast mode in it. The proposed method takes care of the actual trajectory variations over the range of the singular perturbation parameter. Necessary conditions for optimality are also derived. The previous study was done in the continuous time system The present paper extends the previous study to the discrete system and the ${\delta}-operating$ system that unifies the continuous and discrete systems. Advantages of the proposed method are shown in the numerical example.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.260-263
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• 2000

A technique that uses linear prediction to achieve noise reduction in a voice signal which has been mixed with an ambient noise (Signal to Noise (S-N) ratio = about 0dB) is proposed. This noise reduction method which is based on the linear prediction estimates the voice spectrum while ignoring the spectrum of the noise. The performance of the noise reduction method is first examined using the transversal linear predictor filter. However, with this method there is deterioration in the tone quality of the predicted voice due to the low level of the S-N ratio. An additional processing circuit is then proposed so as to adjust the noise reduction circuit with an aim of improving the problem of tone deterioration. Next, we consider a practical application where the effects of round on errors arising from fixed-point computation has to be minimized. This minimization is achieved by using the lattice predictor filter which in comparison to the transversal type, is Down to be less sensitive to the round-off error associated with finite word length operations. Finally, we consider a practical application where noise reduction is necessary. In this noise reduction method, both the voice spectrum and the actual noise spectrum are estimated. Noise reduction is achieved by using the linear predictor filter which includes the control of the predictor filter coefficient’s update.