• Journal of the Korea Society of Computer and Information
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• v.17 no.2
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• pp.149-157
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• 2012

In this thesis, the problem of computing approximate answers to continuous sliding-window joins over data streams when the available memory may be insufficient to keep the entire join state. One approximation scenario is to provide a maximum subset of the result, with the objective of losing as few result tuples as possible. An alternative scenario is to provide a random sample of the join result, e.g., if the output of the join is being aggregated. It is shown formally that neither approximation can be addressed effectively for a sliding-window join of arbitrary input streams. Previous work has addressed only the maximum-subset problem, and has implicitly used a frequency based model of stream arrival. There exists a sampling problem for this model. More importantly, it is shown that a broad class of applications for which an age-based model of stream arrival is more appropriate, and both approximation scenarios under this new model are addressed. Finally, for the case of multiple joins being executed with an overall memory constraint, an algorithm for memory allocation across the join that optimizes a combined measure of approximation in all scenarios considered is provided.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.66-79
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• 2008

Several oxides have recently been reported to have resistance-switching characteristics for nonvolatile memory (NVM) applications. Both binary and ternary oxides demonstrated great potential as resistive-switching memory elements. However, the switching mechanisms have not yet been clearly understood, and the uniformity and reproducibility of devices have not been sufficient for gigabit-NVM applications. The primary requirements for oxides in memory applications are scalability, fast switching speed, good memory retention, a reasonable resistive window, and constant working voltage. In this paper, we discuss several materials that are resistive-switching elements and also focus on their switching mechanisms. We evaluated non-stoichiometric polycrystalline oxides ($Nb_2O_5$, and $ZrO_x$) and subsequently the resistive switching of $Cu_xO$ and heavily Cu-doped $MoO_x$ film for their compatibility with modem transistor-process cycles. Single-crystalline Nb-doped $SrTiO_3$ (NbSTO) was also investigated, and we found a Pt/single-crystal NbSTO Schottky junction had excellent memory characteristics. Epitaxial NbSTO film was grown on an Si substrate using conducting TiN as a buffer layer to introduce single-crystal NbSTO into the CMOS process and preserve its excellent electrical characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.238.1-238.1
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• 2014

이번 연구는 system-on-panel에 적용하기 위한 비휘발성 메모리의 메모리 윈도우 특성 향상에 관한 연구이다. 이를 위해 SiO2/SiNX/SiOXNY의 메모리 구조를 이용하였으며, 채널층으로 투명한 비정질 인듐-주석-아연-산화물을 이용하였다. N형 물질의 특성인 수많은 전자로 인해 erasing의 어려움이 발생하는데 이는 빛과 전압의 동시 인가로 해결하였다. 전하트랩층은 비휘발성 메모리에서 가장 널리 이용되는 질화막을 이용하였으며, SiH4과 NH3의 비율은 8대 1에서 1대 2까지 이용하였다. 이번 연구에서 SiH4과 NH3의 비율이 2대 1일 때 쓰기 전압 +13V와 지우기 전압 -6V에서 약 3.7V의 높은 메모리 윈도우를 얻을 수 있었다.

• Electrical & Electronic Materials
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• v.4 no.3
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• pp.259-266
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• 1991

1.5.mu.m의 찬넬길이를 갖는 short channel 비휘발성 SNOSFET 기억소자를 기존의 CMOS 1 Mbit 공정기술을 이용하여 제작하고 I$_{d}$-V$_{d}$ 및 I$_{d}$- V$_{g}$특성과 스윗칭 및 기억유지특성을 조사하였다. 그 결과 제작한 소자는 논리회로 설계에 적절한 전도특성을 가졌으며 스윗칭시간은 인가전압의 크기에 의존함을 보였다. 그리고 3V의 memory window 크기를 얻기 위해서 V$_{w}$ =+34V, t$_{w}$ =50.mu.sec 및 V$_{e}$=-34V, t$_{e}$=500.mu.sec의 펄스전압으로 각각 write-in과 erase할 수 있었다. 또한 기억상태는 10년이상 유지할 수 있음을 알 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.11
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.725-728
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• 2006

본 논문에서는 Embedded 시스템에서 Windows CE 내에 사용되고 있는 불필요한 메모리를 최소화하고 메모리를 좀 더 효율적으로 관리하기 위한 방안으로 가비지컬렉터를 이용한 메모리관리 방법에 대한 연구이다. Embedded 시스템의 힙 메모리 내에 수집할 수 있는 방법 중 전체수집과, 부분수집에 대하여 살펴본다. 가비지컬렉터가 응용 프로그램에서 더 이상 사용하지 않는 힙 내에 개체가 있는지 확인하고, 힙에 대해 사용할 수 있는 메모리가 더 이상 없을 경우 새 연산자가 Out Of Memory Exception를 실행하게 된다. 실험부분에서 가비지컬렉터의 개체사용 여부를 실험한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.282.1-282.1
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• 2016

The remarkable physical properties of two-dimensional (2D) semiconducting materials such as molybdenum disulfide ($MoS_2$) and tungsten disulfide ($WS_2$) etc. have attracted considerable attentions for future high-performance electronic and optoelectronic devices. The ongoing studies of $MoS_2$ based nonvolatile memories have been demonstrated by worldwide researchers. The opening hysteresis in transfer characteristics have been revealed by different charge confining layer, for instance, few-layer graphene, $MoS_2$, metallic nanocrystal, hafnium oxide, and guanine. However, limited works built their nonvolatile memories using entirely of assembled 2D crystals. This is important in aspect view of large-scale manufacture and vertical integration for future memory device engineering. We report $WS_2$ based nonvolatile memories utilizing functional van der Waals heterostructure in which multi-layered graphene is encapsulated between $SiO_2$ and hexagonal boron nitride (hBN). We experimentally observed that, large memory window (20 V) allows to reveal high on-/off-state ratio (>$10^3$). Moreover, the devices manifest perfect retention of 13% charge loss after 10 years due to large graphene/hBN barrier height. Interestingly, the performance of our memories is drastically better than ever published work related to $MoS_2$ and black phosphorus flash memory technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.7
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• pp.43-49
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• 2000

We proposed ADD(Alternate Directional Delay) circuit technique as the DLL(Delay Locked Loop) circuits which technique is established the data valid window(tDV) in DDR(Double Data Rate) Synchronous DRAM. This technique could be decrease area-overhead which it could generated bidirectional clock simultaneously using only one delay chain block. In this paper for high speed memory with relatively small size. This technique decreased area-overhead more 2 times than SMD(Synchronous Mirror Delay) technique. ADD technique has 50ps-140ps jitter and the operation frequency has 166MHz-66MHz range.(at 2.5V, TYP. condition)