• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.8
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• pp.880-886
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• 2007

We have proposed a new "hybrid" envelope elimination and restoration(EER) transmitter architecture using an efficiency optimized power amplifier(PA) and modified bias modulator. The efficiency of the PA at the average drain voltage is very important for the overall transmitter efficiency because the PA operates mostly at the average power region of the modulation signal. Accordingly, the efficiency of the PA has been optimized at the region. Besides, the bias modulator has been accompanied with the emitter follower for the minimization of memory effect. A saturation amplifier, class $F^{-1}$ is built using a 5-W PEP LDMOSFET for forward-link single-carrier wideband code-division multiple-access(WCDMA) at 1-GHz. For the interlock experiment, the bias modulator has been built with the efficiency of 64.16% and peak output voltage of 31.8 V. The transmitter with the proposed PA and bias modulator has been achieved an efficiency of 44.19%, an improvement of 8.11%. Besides, the output power is enhanced to 32.33 dBm due to the class F operation and the PAE is 38.28% with ACLRs of -35.9 dBc at 5-MHz offset. These results show that the proposed architecture is a very good candidate for the linear and efficient high power transmitter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.2
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• pp.147-152
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• 2012

This paper dealt with the frequency component analysis of acoustic signals produced by corona and series-arc discharges as a diagnostic technique for closed-switchboards. Corona and series-arc discharge were simulated by a needle-plane electrode and an arc generator specified in UL1699, respectively. Acoustic signal was detected by a wideband acoustic sensor with a frequency bandwidth of 4 Hz~100 kHz (-3 dB). We analyzed frequency spectrums of the acoustic signals detected in various discharge conditions. The results showed that acoustic signals mainly exist in ranges from 30 kHz to 60 kHz. From the experimental results, an acoustic detection system which consists of a constant current power supply (CCP), a low noise amplifier (LNA) and a band pass filter was designed and fabricated. The CCP separates the signal component from the DC source of acoustic sensor, and the LNA has a gain of 40 dB in ranges of 280 Hz~320 kHz. The high and the low cut-off frequency are 30 kHz and 60 kHz, respectively. We could detect corona and series-arc discharges without any interference by the acoustic detection system, and the best frequency is considered in ranges of 30 kHz~60 kHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.430-433
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• 2017

This paper presents a S/C/X-band LNA MMIC with resistive feedback structure in 0.25 um GaN HEMT process. The GaN devices have advantages as a high output power device having high breakdown voltage, energy band gap and stability at high temperature. Since the receiver using the GaN device with high linearity can be implemented without a limiter, the noise figure of the receiver can be improved and the size of receiver module can be reduced. The proposed GaN LNA MMIC based on 0.25 um GaN HEMT device is achieved the gain of > 15 dB, the noise figure of < 3 dB, the input return loss of > 13 dB, and the output return loss of > 8 dB in the S/C/X-band. The current consumption of GaN LNA MMIC is 70 mA with the drain voltage 20 V and the gate voltage -3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.242-246
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• 2012

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a $0.18{\mu}m$ CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.2
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• pp.213-219
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• 2012

Recently, we are simultaneously exposed by various electromagnetic sources due to an increase of mobile communication services. However, EMF(Electric, Magnetic and Electromagnetic Field) study has been performed mainly about only single frequency. The objective of this paper is to develop an multiple-frequency exposure system for in vitro experiment. The exposure unit for in vitro experiments was designed by radial transmission line type to get broadband characteristics to generate signals of CDMA at 836.5 MHz and WCDMA at 1950 MHz frequency simultaneously. The modulated signals were delivered to the conical antenna through amplifier, digital attenuator and RF combiner. SAR values were obtained by the averaged values of 3 measured values at 9 points in petri dish using the fiber optic temperature probe. The measured return loss was under -15 dB. For 1 W input power, the mean value and standard deviation of SAR were $0.105{\pm}0.019$ for the CDMA frequency and $0.262{\pm}0.055$ for the WCDMA frequency.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1350-1359
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• 2008

This paper presents a wideband doubly balanced resistive mixer fabricated using $0.5{\mu}m$ GaAs p-HEMT process. Three baluns are employed in the mixer. LO and RF baluns operating over an 8 to 20 GHz range were implemented with Marchand baluns. In order to reduce chip size, the Marchand baluns were realized by the meandering multicoupled line and inductor lines were inserted to compensate for the meandering effect. IF balun was implemented through a DC-coupled differential amplifier. The size of IF balun is $0.3{\times}0.5\;mm^2$ and the measured amplitude and phase unbalances were less than 1 dB and $5^{\circ}$, respectively from DC to 7 GHz. The mixer is $1.7{\times}1.8\;mm^2$ in size, has a conversion loss of 5 to 11 dB, and an output third order intercept(OIP3) of +10 to +15 dBm at 16 dBm LO power for the operating bandwidth.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.684-690
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• 2010

Recently, the NG(Next Generation) system is studied for supporting convergence of various services and multi mode of single terminal. And a demand of user for taking the various services is getting increased, for supporting these services, many systems being able to transmit a large message have been appeared. In the NG system, it has to be supporting the CDMA and WCDMA besides the tele communication systems using OFDM method with single terminal An intergrated system can be improved with adopting of SoC technique. For adopting SoC technique on the intergrated terminal, we have to solve the non linear problem of HPA(High Power Amplifier). Nonlinear characteristic of HPA distorts both amplitude and phase of transmit signal, this distortion cause deep adjacent channel interference. We adopt a polynomial pre-distortion technique for this problem. In this paper, a noble modem design for NG mobile communication service and a method using polynomial pre-distorter with PAPR technique for counterbalancing nonlinear characteristic of the HPA are proposed.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.