• Journal of the Korea Academia-Industrial cooperation Society
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• v.22 no.1
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• pp.321-326
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• 2021

This paper presents a technique to minimize damaged wafers during loading. A thin wafer used in solar cells and semiconductors can be damaged easily. This makes it difficult to separate the wafer due to surface tension between the loaded wafers. A technique for minimizing damaged wafers is to supply compressed air to the wafer and simultaneously apply a small horizontal movement mechanism. The main experimental factors used in this study were the supply speed of wafers, the nozzle pressure of the compressed air, and the suction time of a vacuum head. A higher supply speed of the wafer under the same nozzle pressure and lower nozzle pressure under the same supply speed resulted in a higher failure rate. Furthermore, the damage rate, according to the wafer supply speed, was unaffected by the suction time to grip a wafer. The optimal experiment conditions within the experimental range of this study are the wafer supply speed of 600 ea/hr, nozzle air pressure of 0.55 MPa, and suction time of 0.9 sec at the vacuum head. In addition, the technology improved by the repeatability performance tests can minimize the damaged wafer rate.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.79-83
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• 2007

We have developed a compact and cost-effective camera module on the basis of wafer-scale replication technology. A multiple-layered structure of several aspheric lenses in a mobile camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. We have demonstrated a VGA camera module fabricated by the wafer-scale replication processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having 200 um sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in order to achieve a higher resolution in wafer-scaled lenses for mobile camera modules.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.365-370
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• 2015

Zinc tin oxide transparent thin film transistors (ZTO TTFTs) were fabricated on oxidized $n^+$ Si wafers. The thickness of ~30 nm $Al_2O_3$ films were deposited on the oxidized Si wafers by atomic layer deposition, which acted as the gate insulators of ZTO TTFTs. The $Al_2O_3$ films were rapid-annealed at $400^{\circ}C$, $600^{\circ}C$, $800^{\circ}C$, and $1,000^{\circ}C$, respectively. Active layers of ZTO films were deposited on the $Al_2O_3/SiO_2$ coated $n^+$ Si wafers by rf magnetron sputtering. Mobility and threshold voltage were measured as a function of the rapid-annealing temperature. X-ray photoelectron spectroscopy (XPS) were carried out to observe the chemical bindings of $Al_2O_3$ films. The annealing effects of gate-insulator on the properties of TTFTs were analyzed based on the results of XPS.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.63-63
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• 2003

The nanotopography of silicon wafers has emerged as an important factor in the STI process since it affects the post-CMP thickness deviation (OTD) of dielectric films. Ceria slurry with surfactant is widely applied to STI-CMP as it offers high oxide-to-nitride removal selectivity. Aiming to control the nanotopography impact through ceria slurry characteristics, we examhed the effect of surfactant concentration and abrasive size on the nanotopography impact. The ceria slurries for this study were produced with cerium carbonate as the starting material. Four kinds of slurry with different size of abrasives were prepared through a mechanical treatment The averaged abrasive size for each slurry varied from 70 nm to 290 nm. An anionic organic surfactant was added with the concentration from 0 to 0.8 wt %. We prepared commercial 8 inch silicon wafers. Oxide Shu were deposited using the plasma-enhanced tetra-ethyl-ortho-silicate (PETEOS) method, The films on wafers were polished on a Strasbaugh 6EC. Film thickness before and after CMP was measured with a spectroscopic ellipsometer, ES4G (SOPRA). The nanotopogrphy height of the wafer was measured with an optical interferometer, NanoMapper (ADE Phase Shift)

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• Current Photovoltaic Research
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• v.4 no.2
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• pp.64-67
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• 2016

We investigated the influences of Ag nanoparticle (NP) arrays and surface nanohole (NH) patterns on the optical characteristics of 10-${\mu}m$-thick c-Si wafers using finite-difference time-domain (FDTD) simulations. In particular, we comparatively studied the plasmonic effects of both monomer arrays (MA) and heptamer arrays (HA) consisting of identical Ag NPs. HA improved the optical absorption of the c-Si wafers in much wider wavelength range than MA, with the help of hybridized plasmon modes. The light trapping capability of the NH array pattern is superior to that of the Ag plasmonic NPs. We also found that the addition of the Ag HA on the wafers with surface NH patterns further enhanced optical absorption: the expected short-circuit current density was as high as $34.96mA/cm^2$.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.6
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• pp.65-71
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• 1980

The Sn O2-Si Heterojunction sola cells are Prepared by vacuum deposition of SnO2 on N- and P-type Si - wafers arts the effects of annealing on the Solar cell characteiistics are presented. The existence of optimumannealins temperature for maximum open-circuit voltage and short - circuit current of the solar cell is observed. The optimum tomperature, when low resistivity (7- 2.3 [$\Omega$.cm]) P-and N-type Si -wafers are used, is 500 [$^{\circ}C$] End 400 [$^{\circ}C$] when high resistivity[41-58 [$\Omega$.cm]) P-type Si-wafers are used.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.2
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• pp.144-151
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• 2012

Polishing is not only one of the most frequently adopted processes in modern industries, but also the most critical one to the surface quality of the products such as semi conductor wafers and LED sapphire wafers. With the required specifications for the wafer surface quality getting more and more strengthened, the manufacturers are spending huge amount of cost to renew the machine to meet the enhanced surface specifications. Surface qualities of the wafers are mostly damaged by the structural vibrations of the polishing machines. In this paper, the dynamic characteristics of a wafer polishing machine have been analyzed through the frequency response test and the computer simulation. And the supporting structure of a polishing machine has been investigated to minimize the vibration transmissions, to improve the stability of the machine and further to reduce the defects of the polished products. The result of the study shows that simple design modifications of the supporting structure without altering the main structure of the machine can substantially suppress the vibrations of the machine with negligible expenses.