• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• 한국결정성장학회지
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• 제1권2호
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• pp.79-93
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• 1991

초 고집적 회로의 시대로 접어들면서 지금까지의 금속선 형성 기술 및 배선 재료에 많은 문제점들이 나타나고 있다. 알루미늄의 대체 재료로서 검토되고 있는 구리를, 전기 화학적 방법에 의해 미세 접촉창에 선택적으로 충전함으로써 새로운 금속선 형성 기술을 제시하고자 하였다. 0.75M의 황산구리 수용액을 전해액으로 사용하여 p형 (100) 규소 박판위에 구리 전착막을 형성한 후 Alpha Step, 주사 전자 현미경, 4-탐침법을 사용하여 막의 두께, 입자 크기, 비저항을 측정함으로써 전착 시간, 전류 밀도, 첨가물로 사용한 젤라틴 농도가 전착막의 성질에 미치는 영향에 대해 조사하였다. 평균 전착 속도는 전류 밀도가 $ 2A/dm^2$일 때 0.5-0.6\mu\textrm{m}$/min 였고 구리 입자의 크기는 전류밀도 증가에 따라 증가하였다. 입자 크기 $4000{\AA}$이상에서 얻어진 비저항값은 3-6 Ω.cm였다. 젤라틴을 첨가하여 입자의 크기를 $0.1\mu\textrm{m}$이하로 감소시킴으로써 크기 $1\mu\textrm{m}$이하의 접촉장에 구리를 선택적으로 충전시키는데 성공하였다.

• 센서학회지
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• 제23권3호
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• pp.185-191
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• 2014

The width of depletion region in a varactor diode can be modulated by varying a reverse bias voltage. Thus, the preferred characteristics of depletion capacitance can obtained by the change in the width of depletion region so that it can select only the desirable frequencies. In this paper, the TV tuner varactor diode fabricated by hyper-abrupt profile control technique is presented. This diode can be operated within 3.3 V of driving voltage with capability of UHF band tuning. To form the hyperabrupt profile, firstly, p+ high concentration shallow junction with $0.2{\mu}m$ of junction depth and $1E+20ions/cm^3$ of surface concentration was formed using $BF_2$ implantation source. Simulation results optimized important factors such as epitaxial thickness and dose quality, diffusion time of n+ layer. To form steep hyper-abrupt profile, Formed n+ profile implanted the $PH_3$ source at Si(100) n-type epitaxial layer that has resistivity of $1.4{\Omega}cm$ and thickness of $2.4{\mu}m$ using p+ high concentration Shallow junction. Aluminum containing to 1% of Si was used as a electrode metal. Area of electrode was $30,200{\mu}m^2$. The C-V and Q-V electric characteristics were investigated by using impedance Analyzer (HP4291B). By controlling of concentration profile by n+ dosage at p+ high concentration shallow junction, the device with maximum $L_F$ at -1.5 V and 21.5~3.47 pF at 0.3~3.3 V was fabricated. We got the appropriate device in driving voltage 3.3 V having hyper-abrupt junction that profile order (m factor) is about -3/2. The deviation of capacitance by hyper-abrupt junction with C0.3 V of initial capacitance is due to the deviation of thermal process, ion implantation and diffusion. The deviation of initial capacitance at 0.3 V can be reduced by control of thermal process tolerance using RTP on wafer.

• 센서학회지
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• 제9권1호
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• pp.70-75
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• 2000

단결정 실리콘웨이퍼를 사용한 태양전지 제조에 있어 가장 큰 문제점은 재료의 높은 가격이다. 본 연구에서는 이러한 문제의 해결방안으로 현재 DRAM 소자 제조과정에서 폐기되는 웨이퍼를 리사이클링하여 태양전지를 제작하고 저가의 제조공정과 전지의 특성을 연구하였다. DRAM용 실리콘 웨이퍼는 비저항이 높고 두꺼워 태양전지 재료로서 부적합하나, 본 연구에서는 후면전계 (Back Surface Field) 형성, 표면 Texturing, 반사 방지막 형성 등의 공정들을 조합하여 효율향상을 위한 최적조건을 찾아내고, 두께변화에 따른 효율변화를 조사하였다. 최적화된 위의 모든 조건들을 적용하였을 때, $4\;cm^2$의 면적, $300\;{\mu}m$ 두께를 가지는 태양전지에서 단락전류밀도 ($J_{sc}$)는 $28\;mA/cm^2$, 개방전압 ($V_{oc}$) 0.51V, 충실도(Fill Factor)면에서는 0.53으로 가장 높은 값을 얻었고, 10% 이상의 효율을 확보할 수 있었다. 이와 같은 방법으로 폐기되는 실리콘 웨이퍼들을 재활용하여 실용성이 큰 저가의 단결정 실리콘 태양전지를 제작할 수 있는 방법을 확보할 수 있었다.

• Corrosion Science and Technology
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• 제9권6호
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• 한국진공학회지
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• 제22권4호
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• pp.188-192
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• 2013

반도체 소자의 소형화, 고집적화로 박막의 다층화 및 선폭 감소로 인한 실리콘 웨이퍼와 금속 박막 사이의 확산을 방지하기 위한 많은 연구가 이루어지고 있다. 본 연구는 tungsten (W)을 주 물질로 증착시 nitrogen (N)의 유량을 2.5~10 sccm으로 변화시키며 증착된 확산방지막의 nano-mechanics 특성에 대해 연구하였다. 증착률, 비저항 및 결정학적 특성을 ${\beta}$-ray backscattering spectroscopy, 4-point probe, X-ray diffraction (XRD)을 이용하여 측정한 후 Nano-indenter를 사용하여 nano-mechanics 특성을 조사하였다. 그 결과 질소 가스 유량이 5 sccm 포함된 박막에서 표면 경도(surface hardness)는 10.07 에서 15.55 GPa로 급격하게 증가하였다. 이후 질소가스의 유량이 7.5 및 10 sccm에서는 표면 경도가 각각 12.65와 12.77 GPa로 질소 가스 유량이 5 sccm인 박막보다 표면경도가 상대적으로 감소하였다. 이는 박막 내 결정질과 비정질의 W과 N의 결합 비율의 차이에 의한 영향으로 생각되며, 또한 압축응력에 기인한 스트레스 증가가 원인으로 판단된다.