• 반도체디스플레이기술학회지
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• 제3권3호
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• pp.5-9
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• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 춘계학술대회 논문집
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• pp.509-510
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• 2010

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 2nd Korea-Japan Advanceed Semiconductor Packaging Technology Seminar
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• pp.177-193
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• 2000

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.509-510
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• 2013

• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.41-45
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• 2018

기술의 발전과 전자기기의 소형화와 함께 반도체의 크기는 점점 작아지고 있다. 이와 동시에 반도체 성능의 고도화가 진행되면서 입출력 단자의 밀도는 높아져 패키징의 어려움이 발생하였다. 이러한 문제를 해결하기 위한 방법으로 산업계에서는 팬아웃 웨이퍼 레벨 패키지(FO-WLP)에 주목하고 있다. 또한 FO-WLP는 다른 패키지 방식과 비교해 얇은 두께, 강한 열 저항 등의 장점을 가지고 있다. 하지만 현재 FO-WLP는 생산하는데 몇 가지 어려움이 있는데, 그 중 한가지가 웨이퍼의 휨(Warpage) 현상의 제어이다. 이러한 휨 변형은 서로 다른 재료의 열팽창계수, 탄성계수 등에 의해 발생하고, 이는 칩과 인터커넥트 간의 정렬 불량 등을 야기해 대량생산에 있어 제품의 신뢰성 문제를 발생시킨다. 이러한 휨 현상을 방지하기 위해서는 패키지 재료의 물성과 칩 사이즈 등의 설계 변수의 영향에 대해 이해하는 것이 매우 중요하다. 이번 논문에서는 패키지의 PMC 과정에서 칩의 두께와 EMC의 두께가 휨 현상에 미치는 영향을 유한요소해석을 통해 알아보았다. 그 결과 특정 칩과 EMC가 특정 비율로 구성되어 있을 때 가장 큰 휨 현상이 발생하는 것을 확인하였다.

• 센서학회지
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• 제27권5호
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• pp.300-305
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• 2018

The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

• 한국생산제조학회지
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• 제22권1호
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• pp.168-172
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• 2013

In 3D wafer-stacking technology, one of the major issues is wafer warpage. Especially, The important reason of warpage has been known due to CTE(Coefficient of Thermal Expansion) mismatch between materials. It was too hard to choose how to make the FE model for blanket structured wafer level 3D packaging, because the thickness of each layer in wafer level 3D packaging was too small (micro meter or nano meter scale) comparing with diameter of wafer (6 or 8 inches). In this study, the FE model using the shell element was selected and simulated by the ANSYS WorkBench to investigate effects of the CTE on the warpage. To verify the FE model, it was compared by experimental results.

• 마이크로전자및패키징학회지
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• 제10권3호
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• pp.57-65
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• 2003

본 연구에서는 웨이퍼 레벨 진공 패키징된 MEMS자이로스코프 소자의 신뢰성 시험 및 분석을 통하여 웨이퍼 레벨 진공 패키징의 파괴 메카니즘을 연구하였다. 진공 패키징의 주된 파괴 모드는 누설, 가스투과, 그리고 outgassing이다. 누설은 접합 계면이나 재질의 결함을 통하여 주로 발생되며, 접합폭을 증가시키거나 단결정 실리콘을 사용하면 누설이 감소한다. Outgassing은 실리콘 및 유리기판의 표면 및 내부에서 발생하며 주로 $H_2O$와, $CO_2$, $C_3H_5$ 및 유기 오염물질이었다. Epi-poly의 경우 SOI 웨이퍼보다 약 10배의 outgassing을 발생시킨다. 또한 유리기판을 샌드블라스트 공정을 사용하여 가공한 경우, 약 2.5배의 outgassing 양이 증가한다. Outgassing 제거를 위해서는 접합 전에 웨이퍼를 pre-baking하는 과정이 필수적이며, outgassing의 발생을 최대로 하기 위한 최적의 pre-baking조건은 실리콘과 유리 웨이퍼를 $400^{\circ}C$와 $500^{\circ}C$ 사이에서 pre-baking하는 것이다.