• 전기학회논문지
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• 제67권1호
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• pp.1-7
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• 2018

IEC 61000-3-7 provides guidance for limiting flicker and enabling the connection of fluctuating load installations, that is, producing flicker in MV, HV and EHV power systems. In Korea, the flicker have been restricted by Japanese standard of ${\Delta}V_{10}$ method. ${\Delta}V_{10}$ was developed only for arc furnaces in 1960's. And now it is revealed that it is not suitable for application to other fluctuating load installations through many researches. $P_{st}$ which is a flicker index used in IEC 61000-3-7, indicates visual inconvenience due to voltage fluctuation across large range of frequency and can be applied to fluctuating load installations as well as arc furnaces. In this paper, we introduce how to calculate and assess flicker emission level for the individual fluctuating load installations connected in EHV system and how to manage the emission levels in the power system according to IEC 61000-3-7.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1997년도 춘계학술대회
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• pp.23-26
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• 1997

In exposuring x-rays, we can adjust three variables of kVp, mA and sec. The kVp is one of main factors affecting x-ray quality -peneterability. And miliampere-seconds is directly proportional to x-ray quantity. In this paper, we detected voltage variation of CdS, II-VI group semiconductor compounds, by kVp as the fundamental experiments of designing x-ray dosimeter. We exposured x-ray on the material from 40 to 100 kVp by increasing 2kVp using Shimadazu TH-500-125 Radio-Tex cx-s x-ray machine. We fixed miliampere -seconds to 100mA and 0.2 sec. After acquiring the raw data, we plotted the graph of kVp and voltage variation and figured slope value of 0.093 by regression. The standard deviation of voltage to kVp was 0.22. For the future study, the mAs variation study will be needed to investigate the connections between kVp and mAs in order to design x-ray dosimeter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1070-1072
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• 2001

In recent years, customers and power supplies are interested in power quality. Demands of customers are change from standard quality of distribution power system to various high quality of distribution power system. so, it is necessary to apply power quality compensator, in our project, we develop the power quality compensator of 150kVA which compensates power factor and voltage sag, interruption. it is very frequently occurred power qualify problems[1,2]. As a series and shunt compensator, power quality compensator consists of two inverters with common do link capacitor bank. It compensates the current quality in the shunt part and the voltage qualify in the series part. In this paper we present the design and control algorithm of power quality compensator. As a control algorithm is implemented by digital controller, we consider sample-and-hold of signals. In this simulation, we use EMTDC/PSCAD V3.0 software which can simulate instantaneous voltage and current.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.29-34
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• 2017

A CMOS-based temperature sensor is proposed for low-voltage and low-power on-chip thermal monitoring applications. The proposed temperature sensor converts a proportional to absolute temperature (PTAT) current to a PTAT frequency using an integrator and hysteresis comparator. In addition, it operates in the subthreshold region, allowing reduced power consumption. The proposed temperature sensor was fabricated in a standard 90 nm CMOS technology. Measurement results of the proposed temperature sensor show a temperature error of between -0.81 and $+0.94^{\circ}C$ in the temperature range of 0 to $70^{\circ}C$ after one-point calibration at $30^{\circ}C$, with a temperature coefficient of $218Hz/^{\circ}C$. Moreover, the measured energy of the proposed temperature sensor is 36 pJ per conversion, the lowest compared to prior works.

• 전기전자학회논문지
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• 제8권1호
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• pp.47-53
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• 2004

본 논문에서는 3치 논리 게이트를 바탕으로 하는 3치 데이터 처리를 위한 3치 flip-flop을 설계하였다. 제안한 flip-flop들은 3치 전압 모드 NMAX, NMIN, INVERTER 게이트를 사용하여 설계하였다. 또한 CMOS 기술을 사용하였고 다른 게이트들 보다 낮은 공급 전압과 낮은 전력소모 특성을 포함하고 있다. 제안한 회로는 0.35um 표준 CMOS 공정에서 설계되었고 3.3v의 공급 전압원을 사용하였다. 제안된 3치 flip-flop 구조는 3치 논리 게이트를 사용하여 VLSI 구현에 적합하고 높은 모듈성의 장점을 갖고 있다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 A
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• pp.351-353
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• 2004

In recent years, customers and power supplies are interested in power quality. Demands of customers are change from standard quality of distribution power system to various high quality of distribution power system. so, it is necessary to apply power quality compensator. in our project, we develop the UPQC(Unfied Power Quality Compensator of 45kVA which compensates power factor and voltage sag, interruption. it is very frequently occurred power quality $problems^{[1-3]}$ As a series and shunt compensator, UPQC consists of two inverters with common do link capacitor bank. It compensates the current quality in the shunt part and the voltage quality in the series part. In this paper, we present the design and control algorithm for 4SkVA UPQC system. As a control algorithm is implemented by digital controller, we consider sample-and-hold of signals. In this simulation, we use EMTDC/PSCAD V3.0 software which can simulate instantaneous voltage and current.

• 한국전기전자재료학회논문지
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• 제23권4호
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• 전기전자학회논문지
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• 제3권2호
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• pp.161-167
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• 1999

표준 2-poly CMOS 공정을 이용하여 3-입력 neuron-MOSFET의 인버터와 증가형 소자를 사용한 3비트 D/A 변환기를 설계 제작하였다. Neuron-MOSFET를 사용한 인버터의 전압전달 특성곡선과 잡음여유를 일반 CMOS 인버터와 같은 방법으로 측정분석하였다. 결합계수가 전압전달 특성곡선과 잡음여유에 미치는 영향을 이론적으로 계산하여 neuron-MOSFET 인버터의 게이트 산화층 두께와 입력게이트 레이아웃에 대한 설계 가이드라인을 설정하였다. 입력게이트 중 하나를 제어게이트로 사용하므로 offset전압이 없는 neuron-MOSFET D/A 변환기를 설계 제작할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

• Journal of Electrical Engineering and Technology
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• 제11권3호
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• pp.675-682
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• 2016

Sudden voltage drops and outages frequently disturb the operation of sensitive loads for domestic, commercial, and industrial use. In some cases, these events may even impair the functioning of relevant equipment. To maintain power under such conditions, a UPS system is usually installed. Once a disturbance happens at the grid side, the line-interactive UPS system takes over the load to prevent an interruption. But, due to magnetic saturation of the transformer, a significant inrush current may occur for the transformer-coupled loads during this transition. The generation of such transient currents may in turn decrease the line voltage and activates over-current protecting devices of the system. In this work, a cost-effective, line-interactive UPS system is proposed that eliminates the inrush current phenomenon associated with transformer-coupled loads. The strategy was implemented by connecting a standard current-regulated voltage source inverter (CRVSI) to the secondary winding of the load transformer. During any transient condition at the grid side, the load current is monitored and regulated to achieve either seamless compensation of the load current or complete transferal of load from grid to the inverter. Experimental results were obtained for a prototype under all possible operating conditions so as to validate the performance of the proposed topology.