• 제목/요약/키워드: voltage standard

검색결과 977건 처리시간 0.027초

Electric Arc Furnace Voltage Flicker Mitigation by Applying a Predictive Method with Closed Loop Control of the TCR/FC Compensator

  • Kiyoumarsi, Arash;Ataei, Mohhamad;Hooshmand, Rahmat-Allah;Kolagar, Arash Dehestani
    • Journal of Electrical Engineering and Technology
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    • 제5권1호
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    • pp.116-128
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    • 2010
  • Modeling of the three phase electric arc furnace and its voltage flicker mitigation are the purposes of this paper. For modeling of the electric arc furnace, at first, the arc is modeled by using current-voltage characteristic of a real arc. Then, the arc random characteristic has been taken into account by modulating the ac voltage via a band limited white noise. The electric arc furnace compensation with static VAr compensator, Thyristor Controlled Reactor combined with a Fixed Capacitor bank (TCR/FC), is discussed for closed loop control of the compensator. Instantaneous flicker sensation curves, before and after accomplishing compensation, are measured based on IEC standard. A new method for controlling TCR/FC compensator is proposed. This method is based on applying a predictive approach with closed loop control of the TCR/FC. In this method, by using the previous samples of the load reactive power, the future values of the load reactive power are predicted in order to consider the time delay in the compensator control. Also, in closed loop control, two different approaches are considered. The former is based on voltage regulation at the point of common coupling (PCC) and the later is based on enhancement of power factor at PCC. Finally, in order to show the effectiveness of the proposed methodology, the simulation results are provided.

송전철탑 Compact화에 따른 전기환경 영향 연구 (A Study on the Environmental Effects of Compact Tower in Transmission Line)

  • 이정원;이원교;이동일
    • 한국전기전자재료학회논문지
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    • 제23권8호
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    • pp.645-650
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    • 2010
  • The continuous increase demand for electric power leads to the additional construction of transmission facilities, but it is not easy to acquire right-of-way for transmission facilities. Therefor, there is a need for compact tower that can be built on a narrow right-of-way the compact tower with polymer insulation arm is a solution. It can be upgrading conventional 154 kV transmission line voltages to 345 kV levels. However transmission voltage is increasing, environment interference (corona noise, radio interference, etc.) will occur gradually. This environment interference is depending on the electrical clearances of tower and configuration of conductors. Therefore the analysis of the factors of environmental interference is necessary in order to upgrading transmission voltage. This paper presents the design factor of a compact tower to meet the environmental interference standard.

진단방사선촬영에서 광자극형광선량계의 에너지의존성에 대한 보정인자 (Correction Factor for the Eenergy Dependence of a Optically Stimulated Luminescent Dosimeter in Diagnostic Radiography)

  • 김종언;임인철;이효영
    • 한국방사선학회논문지
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    • 제5권5호
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    • pp.261-265
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    • 2011
  • 이 연구의 목적은 진단방사선촬영에서 환자의 피부선량을 측정하는 나노도트선량계의 에너지의존성에 대한 보정인자들을 구하는 것이다. 보정인자들은 랜다우어사에서 제공한 팬텀 정에 관한 X-선에 상대적인 선량계의 에너지반응그래프와 로사도 등이 발표한 IEC의 RQR 표준방사선 품질들에 대한 평균에너지 값들을 사용하여 구하였다. 결과들은 관전압 40-150 kVp에서 1-1.33의 보정인자들을 나타냈다. 얻어진 보정인자들은 각 관전압에서 정확한 피부선량 측정을 위하여 임상에 사용하는데 유용할 것으로 생각된다.

Telescopic 증폭기를 이용한 고속 LVDS I/O 인터페이스 설계 (Design of a High-Speed LVDS I/O Interface Using Telescopic Amplifier)

  • 유관우;김정범
    • 대한전자공학회논문지SD
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    • 제44권6호
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    • pp.89-93
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    • 2007
  • 본 논문은 3.3V, $0.35{\mu}m$ CMOS 기술을 이용하여 I/O 인터페이스를 설계, 검증하였다. LVDS (low-voltage differential signaling)는 차동전송 방식과 저 전압의 스윙으로 저 전력 고속의 데이터를 전송할 수 있다. 본 논문은 기존의 차동증폭기나 감지 증폭기를 사용한 LVDS와 달리 telescopic 증폭기를 이용하여 2.3 Gbps의 빠른 전송속도를 갖는 LVDS 고속 인터페이스를 구현하였다. LVDS의 표준을 모두 충족하였고 25.5mW의 전력소모를 갖는다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction

  • Chung, Yeon-Bae
    • 전기전자학회논문지
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    • 제16권3호
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    • pp.265-273
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    • 2012
  • Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

1.5 V Sub-mW CMOS Interface Circuit for Capacitive Sensor Applications in Ubiquitous Sensor Networks

  • Lee, Sung-Sik;Lee, Ah-Ra;Je, Chang-Han;Lee, Myung-Lae;Hwang, Gunn;Choi, Chang-Auck
    • ETRI Journal
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    • 제30권5호
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    • pp.644-652
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    • 2008
  • In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

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초음파 의료 영상시스템용 고집적 아날로그 Front-End 집적 회로 (A Highly-Integrated Analog Front-End IC for Medical Ultrasound Imaging Systems)

  • 아디탸 바누아지;차혁규
    • 전자공학회논문지
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    • 제50권12호
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    • pp.49-55
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    • 2013
  • 초음파 의료 영상 응용 분야를 위한 고전압 고집적 아날로그 front-end 집적회로를 0.18-${\mu}m$ 표준 CMOS 반도체 공정을 이용하여 구현하였다. 제안 된 아날로그 front-end 집적회로는 2.6 MHz에서 15 Vp-p 전압까지 동작하는 트랜지스터 stacking구조를 이용한 고전압 펄서와, 저전압에서 동작하는 저잡음 transimpedance 증폭기, 그리고 송신부와 수신부의 분리를 위한 고전압 차단 스위치로 구성되어 있다. 설계 된 집적회로는 $0.15mm^2$ 이하의 작은 면적을 사용함으로써 휴대용 영상 시스템을 포함한 다중 어레이 초음파 의료 영상 시스템에 적용이 가능하다.

GMAW 공정에서 아크 안정성의 실시간 측정 (Real-time estimation of arc stability in GMAW process)

  • 원윤재;부광석;조형석
    • Journal of Welding and Joining
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    • 제8권1호
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    • pp.31-42
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    • 1990
  • Arc must be stable during welding first of all other factors for obtaining sound weldment, especially in the automation of welding process. Arc stability is somewhat sophisticated phenomenon which is not clearly defined yet. In consumable electrode welding, the voltage and current variation due to metal transfer enables to assess arc stability. Recently, statistical analyses of the voltage and current waveform factors are performed to assess the degress of arc stability which is assessed and controlled by operator's own experience by now. But, considering the increasing need and the trend of automation of welding process, it is necessary to monitor arc stability in real-time. In this sutdy, the modified stability index composed of two voltage and current wvaeform factors (arc time and short circuit time) reduced from four factors (arc time, short circuit time, average arc current and average short circuit current) in Mita's index by the welding electrical circuit modeling is proposed and verified by experiments to be well estimating arc stability in the static sense. Also, the recursive calculation form estimating present arc stability in the dynamic sense is developed for real-time estimation. The results of applying the recursive index during welding show good estimation of arc stability in real-time. Therefore, the results of this study offers the mean for real-time control arc stability.

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저압 전원계통 접지방식별 뇌서지보호성능 (Protection ability for lightning surge according to the grounding system of low voltage power systems)

  • 이복희;이규선;최종혁;유양우;김동성;강성만;안창환
    • 한국조명전기설비학회:학술대회논문집
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    • 한국조명전기설비학회 2009년도 추계학술대회 논문집
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    • pp.343-346
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    • 2009
  • The grounding system of low voltage power systems is TT grounding system in Korea. In order to follow the international standard, TN grounding system is adopted. However, the performance of grounding systems has not been evaluated. This paper deals with the experimental results of protection ability of grounding system when lightning surge invades to the neutral line of low voltage power system. As a result, the TT grounding system is most frail for the lightning surge and it does not protect the electrical devices. On the other hand, the TN grounding system perfectly protects the electrical equipment and prevents the electric shock for human through the equipotential bonding. In case of TN system with supplement grounding, it is very important to lower the supplement grounding resistance to protect the electrical equipment and electric shock for human.

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PMOS 소자가 삽입된 부분웰 구조의 N형 SCR 소자에서 정전기 보호 성능 향상을 위한 최적의 CPS 이온주입에 대한 연구 (Study on the Optimal CPS Implant for Improved ESD Protection Performance of PMOS Pass Structure Embedded N-type SCR Device with Partial P-Well Structure)

  • 양준원;서용진
    • 한국위성정보통신학회논문지
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    • 제10권4호
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    • pp.1-5
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    • 2015
  • PPS 소자가 삽입된 부분웰 구조의 N형 실리콘 제어 정류기(NSCR_PPS) 소자에서 정전기 보호 성능의 향상을 위한 CPS 이온주입조건의 최적화에 대해 연구하였다. 종래의 NSCR 표준소자는 on-저항, 스냅백 홀딩 전압 및 열적 브레이크다운 전압이 너무 낮아 정전기 보호소자의 필요조건을 만족시키지 못해 적용이 어려웠으나, 본 연구에서 제안하는 CPS 이온주입과 부분웰 이온주입을 동시에 적용한 변형 설계된 소자의 경우 스냅백 홀딩 전압을 동작전압 이상으로 증가시킬 수 있는 향상된 정전기 보호성능을 나타내어 고전압 동작용 마이크로 칩의 정전기보호 소자로 적용 가능함을 확인하였다.