• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.525-526
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• 2008

This paper proposes a new high-speed level shifter using a special high voltage device with low threshold voltage. Also, novel low voltage swing method is proposed. The high voltage device is a standard LDMOS(Laterally Diffused MOS) device in a $0.18{\mu}m$ CMOS process without adding extra mask or process step to realize it. A level shifter uses 5V LDMOSs as voltage clamps to protect 1.8V NMOS switches from high voltage stress the gate oxide. Also, level-up transition from 1.8V to 5V takes only 1.5ns in time. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.

• ETRI Journal
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• 제39권3호
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• 신재생에너지
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• 제9권2호
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• pp.51-57
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• 2013

The Grid code is being strengthen as increase of renewable energy ratio. Especially, the grid connection regulations are continuously being updated for stable operation of power grids. Static grid support and Dynamic grid support must make an accurate measure at Grid connected point because they needs control algorithm individually. It has to exactly measure voltage including switching ripple at the output of the inverter generating system. In addition, it is necessary to have an accurate voltage measurement when the situation rapidly changing the grid impedance is caused by the input of serial impedance of transformer and line impedance as well as Grid Fault Device. In this paper, We propose a new detection method of grid voltage to calculate accurately the r.m.s voltage of the grid connection point along the standard required by the low voltage regulation. We verified performance through simulation grid fault device.

• 전기학회논문지
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• 제56권11호
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• pp.1910-1920
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• 2007

This paper deals with the optimal evaluation algorithms for voltage regulation in the case where new dispersed generations(DG) are operated in distribution systems. It is very difficult and complicated to handle the interconnection issues for proper voltage managements, because professional skills and enormous amounts of data for the evaluations are required. The typical evaluation algorithms mainly depending on human ability and quality of data acquired, inevitably cause the different results for the same issue, so unfair and subjective evaluations are unavoidable. In order to overcome these problems, the paper proposes reasonable and general algorithms based on the standard model system and proper criterion, which offers the fair and objective evaluations in any case. The proposed algorithms are divided by two main themes. One is an optimal algorithm for the voltage control of multiple voltage regulators in order to deliver suitable voltage to as many customers as possible, and the other is a proper evaluation algorithm for the voltage management at normal and emergency conditions. The results from a case study show that the proposed methods can be a practical tool for the voltage management in distribution systems including dispersed sources.

• Journal of Electrical Engineering and Technology
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• 제8권2호
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• pp.206-214
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• 2013

This paper proposes a new method for monitoring local voltage stability using the saddle node bifurcation set or loadability boundary in two dimensional power parameter space. The method includes three main steps. First step is to determine the critical buses and the second step is building the static voltage stability boundary or the saddle node bifurcation set. Final step is monitoring the voltage stability through the distance from current operating point to the boundary. Critical buses are defined through the right eigenvector by direct method. The boundary of the static voltage stability region is a quadratic curve that can be obtained by the proposed method that is combining a variation of standard direct method and Thevenin equivalent model of electric power system. And finally the distance is computed through the Euclid norm of normal vector of the boundary at the closest saddle node bifurcation point. The advantage of the proposed method is that it gets the advantages of both methods, the accuracy of the direct method and simple of Thevenin Equivalent model. Thus, the proposed method holds some promises in terms of performing the real-time voltage stability monitoring of power system. Test results of New England 39 bus system are presented to show the effectiveness of the proposed method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• 한국전기전자재료학회논문지
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• 제24권3호
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• pp.250-255
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• 2011

This paper dealt with the design, fabrication and application of a risk voltage measurement system (RVMS) which analyzes the step and touch voltages in electrical grounding systems. The RVMS supply 300 V and 1.4 A in ranges from 40 Hz to 1 kHz as the test power source. A DAQ module having resolution of 400 kS/s and 16 bit is equipped with 7 inputs for measuring voltage and current. Also, a noise elimination algorithm of digital filter was applied to reduce the measurement error caused by external noises as a commercial frequency current. The performance of the RVMS was evaluated by measurement of the step and touch voltage according to the IEEE standard 80 and 81 in a grounding system with a 10 m counterpoise. The result showed that the RVMS analyzes the risk voltage with the error below 5%.

• 전기학회논문지
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• 제57권3호
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• pp.344-353
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• 2008

To apply the appropriate new grounding system to domestic power system, safety has to be guaranteed under the given circumstances. It is not possible to decide the safety of grounding systems by the experimental test because safety experiments directly relate to the human life and the installed electric machines. Therefore, the computer simulation program to decide the safety of grounding systems based on the IEC standard systems, has to be developed. This paper proposes the computer simulation based method to decide the safety of grounding system with the concepts of touch voltage, step voltage, human resistivity, and applied electric current according to the several conditions of human body located in the corresponding grounding systems. The proposed method is implemented by Matlab/Simulink and Visual C++ programming tools for its visualization.

• Journal of Welding and Joining
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• 제16권6호
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• pp.52-58
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• 1998

The effect of Si content in welding wires on th arc stability was investigate, in the region of short circuit transfer and spray transfer. In the region of short circuit transfer, with increasing Si content, average arcing time and average short circuit time were increased. Therefore, droplet transfer frequency was decreased, due to the increase of arcing time and peak current at the moment of arc-reiginition was increased, due to the increase of short circuit time. In the region of spray transfer, the fluctuations of arc current and arc voltage was the most stable in wire with Si content of about 00.60 wt.%.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.21-24
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• 2002

This paper presents a fully integrated, wide tuning range differential CMOS voltage-controlled oscillator, tuned by pMOS-varactors. VCO utilizing a novel tuning scheme is reported. Both coarse digital tuning and fine analog tuning are achieved using pMOS-varactors. The VCO were implemented in a 0.18-fm standard CMOS process. The VCO tuned from 1.8㎓ to 2.55㎓ through 2-bit digital and analog input. At 1.8V power supply voltage and a total power dissipation of 8mW, the VCO features a phase noise of -126㏈c/㎐ at 3㎒ frequency offset.