• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.1
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• pp.1-7
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• 2018

IEC 61000-3-7 provides guidance for limiting flicker and enabling the connection of fluctuating load installations, that is, producing flicker in MV, HV and EHV power systems. In Korea, the flicker have been restricted by Japanese standard of ${\Delta}V_{10}$ method. ${\Delta}V_{10}$ was developed only for arc furnaces in 1960's. And now it is revealed that it is not suitable for application to other fluctuating load installations through many researches. $P_{st}$ which is a flicker index used in IEC 61000-3-7, indicates visual inconvenience due to voltage fluctuation across large range of frequency and can be applied to fluctuating load installations as well as arc furnaces. In this paper, we introduce how to calculate and assess flicker emission level for the individual fluctuating load installations connected in EHV system and how to manage the emission levels in the power system according to IEC 61000-3-7.

• Proceedings of the KOSOMBE Conference
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• v.1997 no.05
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• pp.23-26
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• 1997

In exposuring x-rays, we can adjust three variables of kVp, mA and sec. The kVp is one of main factors affecting x-ray quality -peneterability. And miliampere-seconds is directly proportional to x-ray quantity. In this paper, we detected voltage variation of CdS, II-VI group semiconductor compounds, by kVp as the fundamental experiments of designing x-ray dosimeter. We exposured x-ray on the material from 40 to 100 kVp by increasing 2kVp using Shimadazu TH-500-125 Radio-Tex cx-s x-ray machine. We fixed miliampere -seconds to 100mA and 0.2 sec. After acquiring the raw data, we plotted the graph of kVp and voltage variation and figured slope value of 0.093 by regression. The standard deviation of voltage to kVp was 0.22. For the future study, the mAs variation study will be needed to investigate the connections between kVp and mAs in order to design x-ray dosimeter.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1070-1072
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• 2001

In recent years, customers and power supplies are interested in power quality. Demands of customers are change from standard quality of distribution power system to various high quality of distribution power system. so, it is necessary to apply power quality compensator, in our project, we develop the power quality compensator of 150kVA which compensates power factor and voltage sag, interruption. it is very frequently occurred power qualify problems[1,2]. As a series and shunt compensator, power quality compensator consists of two inverters with common do link capacitor bank. It compensates the current quality in the shunt part and the voltage qualify in the series part. In this paper we present the design and control algorithm of power quality compensator. As a control algorithm is implemented by digital controller, we consider sample-and-hold of signals. In this simulation, we use EMTDC/PSCAD V3.0 software which can simulate instantaneous voltage and current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.29-34
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• 2017

A CMOS-based temperature sensor is proposed for low-voltage and low-power on-chip thermal monitoring applications. The proposed temperature sensor converts a proportional to absolute temperature (PTAT) current to a PTAT frequency using an integrator and hysteresis comparator. In addition, it operates in the subthreshold region, allowing reduced power consumption. The proposed temperature sensor was fabricated in a standard 90 nm CMOS technology. Measurement results of the proposed temperature sensor show a temperature error of between -0.81 and $+0.94^{\circ}C$ in the temperature range of 0 to $70^{\circ}C$ after one-point calibration at $30^{\circ}C$, with a temperature coefficient of $218Hz/^{\circ}C$. Moreover, the measured energy of the proposed temperature sensor is 36 pJ per conversion, the lowest compared to prior works.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Proceedings of the KIEE Conference
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• summer
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• pp.351-353
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• 2004

In recent years, customers and power supplies are interested in power quality. Demands of customers are change from standard quality of distribution power system to various high quality of distribution power system. so, it is necessary to apply power quality compensator. in our project, we develop the UPQC(Unfied Power Quality Compensator of 45kVA which compensates power factor and voltage sag, interruption. it is very frequently occurred power quality $problems^{[1-3]}$ As a series and shunt compensator, UPQC consists of two inverters with common do link capacitor bank. It compensates the current quality in the shunt part and the voltage quality in the series part. In this paper, we present the design and control algorithm for 4SkVA UPQC system. As a control algorithm is implemented by digital controller, we consider sample-and-hold of signals. In this simulation, we use EMTDC/PSCAD V3.0 software which can simulate instantaneous voltage and current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.161-167
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• 1999

3-input neuron-MOSFET inverters and 3-bit D/A converters using enhancement type device have been designed and fabricated by using standard 2-poly CMOS process. The voltage transfer curve and the noise margin of neuron-MOSFET inverters have been measured and characterized as the same method in normal CMOS inverters. From the theoretical calculation of the effects of coupling ratio on the voltage transfer curve and noise margin, we set up the design guideline for the gate oxide thickness and input gate layout in neuron-MOSFET inverters. BT using one of input gates as a control gate, we can design and fabricate the neuron-MOSFET D/A converter without offset voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.675-682
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• 2016

Sudden voltage drops and outages frequently disturb the operation of sensitive loads for domestic, commercial, and industrial use. In some cases, these events may even impair the functioning of relevant equipment. To maintain power under such conditions, a UPS system is usually installed. Once a disturbance happens at the grid side, the line-interactive UPS system takes over the load to prevent an interruption. But, due to magnetic saturation of the transformer, a significant inrush current may occur for the transformer-coupled loads during this transition. The generation of such transient currents may in turn decrease the line voltage and activates over-current protecting devices of the system. In this work, a cost-effective, line-interactive UPS system is proposed that eliminates the inrush current phenomenon associated with transformer-coupled loads. The strategy was implemented by connecting a standard current-regulated voltage source inverter (CRVSI) to the secondary winding of the load transformer. During any transient condition at the grid side, the load current is monitored and regulated to achieve either seamless compensation of the load current or complete transferal of load from grid to the inverter. Experimental results were obtained for a prototype under all possible operating conditions so as to validate the performance of the proposed topology.