• Journal of Electrical Engineering and Technology
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• v.5 no.1
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• pp.116-128
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• 2010

Modeling of the three phase electric arc furnace and its voltage flicker mitigation are the purposes of this paper. For modeling of the electric arc furnace, at first, the arc is modeled by using current-voltage characteristic of a real arc. Then, the arc random characteristic has been taken into account by modulating the ac voltage via a band limited white noise. The electric arc furnace compensation with static VAr compensator, Thyristor Controlled Reactor combined with a Fixed Capacitor bank (TCR/FC), is discussed for closed loop control of the compensator. Instantaneous flicker sensation curves, before and after accomplishing compensation, are measured based on IEC standard. A new method for controlling TCR/FC compensator is proposed. This method is based on applying a predictive approach with closed loop control of the TCR/FC. In this method, by using the previous samples of the load reactive power, the future values of the load reactive power are predicted in order to consider the time delay in the compensator control. Also, in closed loop control, two different approaches are considered. The former is based on voltage regulation at the point of common coupling (PCC) and the later is based on enhancement of power factor at PCC. Finally, in order to show the effectiveness of the proposed methodology, the simulation results are provided.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.645-650
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• 2010

The continuous increase demand for electric power leads to the additional construction of transmission facilities, but it is not easy to acquire right-of-way for transmission facilities. Therefor, there is a need for compact tower that can be built on a narrow right-of-way the compact tower with polymer insulation arm is a solution. It can be upgrading conventional 154 kV transmission line voltages to 345 kV levels. However transmission voltage is increasing, environment interference (corona noise, radio interference, etc.) will occur gradually. This environment interference is depending on the electrical clearances of tower and configuration of conductors. Therefore the analysis of the factors of environmental interference is necessary in order to upgrading transmission voltage. This paper presents the design factor of a compact tower to meet the environmental interference standard.

• Journal of the Korean Society of Radiology
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• v.5 no.5
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• pp.261-265
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• 2011

The purpose of this study is to calculate correction factors for energy dependence of a nanoDotdosimeter to measure patient's skin dose in diagnostic radiography. The correction factors were calculated by using the values of mean energy for the RQR standard radiation qualities of IEC publicated by Rosado et al. and the energy response graph of dosimeter relative X-ray on phantom calibration provided by landaur corporation. Results showed the correction factors of 1-1.33 over the tube voltage range of 40-50 kVp. Acquired correction factors are considered to be useful in the clinics for the measurement of accurate skin dose at each tube voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• ETRI Journal
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• v.30 no.5
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.49-55
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• 2013

A high-voltage highly-integrated analog front-end (AFE) IC for medical ultrasound imaging applications is implemented using standard 0.18-${\mu}m$ CMOS process. The proposed AFE IC is composed of a high-voltage (HV) pulser utilizing stacked transistors generating up to 15 Vp-p pulses at 2.6 MHz, a low-voltage low-noise transimpedance preamplifier, and a HV switch for isolation between the transmit and receive parts. The designed IC consumes less than $0.15mm^2$ of core area, making it feasible to be applied for multi-array medical ultrasound imaging systems, including portable handheld applications.

• Journal of Welding and Joining
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• v.8 no.1
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• pp.31-42
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• 1990

Arc must be stable during welding first of all other factors for obtaining sound weldment, especially in the automation of welding process. Arc stability is somewhat sophisticated phenomenon which is not clearly defined yet. In consumable electrode welding, the voltage and current variation due to metal transfer enables to assess arc stability. Recently, statistical analyses of the voltage and current waveform factors are performed to assess the degress of arc stability which is assessed and controlled by operator's own experience by now. But, considering the increasing need and the trend of automation of welding process, it is necessary to monitor arc stability in real-time. In this sutdy, the modified stability index composed of two voltage and current wvaeform factors (arc time and short circuit time) reduced from four factors (arc time, short circuit time, average arc current and average short circuit current) in Mita's index by the welding electrical circuit modeling is proposed and verified by experiments to be well estimating arc stability in the static sense. Also, the recursive calculation form estimating present arc stability in the dynamic sense is developed for real-time estimation. The results of applying the recursive index during welding show good estimation of arc stability in real-time. Therefore, the results of this study offers the mean for real-time control arc stability.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2009.10a
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• pp.343-346
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• 2009

The grounding system of low voltage power systems is TT grounding system in Korea. In order to follow the international standard, TN grounding system is adopted. However, the performance of grounding systems has not been evaluated. This paper deals with the experimental results of protection ability of grounding system when lightning surge invades to the neutral line of low voltage power system. As a result, the TT grounding system is most frail for the lightning surge and it does not protect the electrical devices. On the other hand, the TN grounding system perfectly protects the electrical equipment and prevents the electric shock for human through the equipotential bonding. In case of TN system with supplement grounding, it is very important to lower the supplement grounding resistance to protect the electrical equipment and electric shock for human.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.