• Title/Summary/Keyword: voltage standard

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A 2㎓, Low Noise, Low Power CMOS Voltage-Controlled Oscillator Using an Optimized Spiral Inductor for Wireless Communications (최적화된 나선형 인덕터를 이용한 이동 통신용 저잡음. 저전력 2㎓ CMOS VCO 설계에 관한 연구)

  • 조제광;이건상;이재신;김석기
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.283-286
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    • 1999
  • A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.

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Fabrication of Thick Periodically-poled Lithium Niobate Crystals by Standard Electric Field Poling and Direct Bonding

  • Kim, Byoung-Joo;Kim, Chung-Sik;Kim, Dong-Jin;Lim, Hwan-Hong;Park, Sung-Kyun;Cha, Myoung-Sik;Kim, Kyung-Jo
    • Journal of the Optical Society of Korea
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    • v.14 no.4
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    • pp.420-423
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    • 2010
  • We fabricated 1 mm-thick periodically-poled lithium niobate (PPLN) crystals by using a high-voltage amplifier for standard electric field poling combined with a voltage multiplier. Furthermore, two 1 mm-thick PPLNs were directly bonded to make a 2 mm-thick PPLN. The large aperture allowed broad angular tuning, and a broad spectral range of quasi-phase matched second-harmonic generation can be achieved in a single channel. High-power applications are also expected.

Analog Signal Conditioner Using Fuzzy Logic Technique

  • Maipradith, N.;Riewruja, V.;Chaikla, A.;Julsereewong, P.;Ukakimaparn, P.
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.472-472
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    • 2000
  • An analog signal conditioner using fuzzy logic technique, which has multiple-input and multiple-output terminals, is proposed in this paper. The proposed signal conditioner can be employed to linearly translate the level of signals to a standard voltage signal (1-5V) and convert the form of signals to a standard current signal (4-20mA). The implementation method based on the use of a commercial 8-bit microcontroller, the analog-to-digital (A/D) converters, the digital-to-analog (D/A) converters and the voltage-to-current (V/I) converter. The simulation result and the experimental results are presented, which further confirm the feasibility of this approach.

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Temporary calibration procedures for high-current measuring system (대전류 측정시스템에 대한 잠정적 교정절차)

  • Shin, Y.J.;Kim, I.K.;Kim, M.K.
    • Proceedings of the KIEE Conference
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    • 2001.07a
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    • pp.440-442
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    • 2001
  • Calibration procedure of high-current measuring system has been promoted to ensure the traceability of national of international standard with the similar method of high-voltage measuring system. This paper introduces general procedure to establish the traceability and type & performance tests for current-voltage transformer, transmission system, recorder and evaluation procedure as the result of intercomparison tests performed 7 laboratories of Europe, and introduces briefly the test method of itemized list from type & performance tests. So we would apply the standard as the criteria that can be enforced temporarily in korea.

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Machine learning-based design automation of CMOS analog circuits using SCA-mGWO algorithm

  • Vijaya Babu, E;Syamala, Y
    • ETRI Journal
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    • v.44 no.5
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    • pp.837-848
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    • 2022
  • Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

Establishment of Evaluation System for 40,000 A Rogowski Coil (40,000 A 로고스키 코일 평가 시스템 구축)

  • Kim, Yoon-Hyoung;Han, Sang-Gil;Jung, Jae-Kap;Kang, Jeon-Hong;Lee, Sang-Hwa;Han, Sang-Ok
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.58 no.2
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    • pp.202-206
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    • 2009
  • Evaluation system for calibrating Rogowski coiI(RC) up to primary current of 40,000 A have been established. The system consists of 40,000 A AC high current source, current transformer(CT) comparator, standard CT, RC under test, voltage to current convertor(VCC), buffer and CT burden. An AC high current is applied to the primary windings of both the standard CT and the RC under test, and then the CT comparator measures the ratio error and the phase displacement by comparing the secondary current of the standard CT with output current of VCC. For testing of RC, we have evaluated two RCs under test of primary current ranges of 0 A ${\sim}$ 2,000 A and 0 A ${\sim}$ 40,000 A with the accuracy class of 1 %. The extended uncertainty is 0.02 % ${\sim}$ 0.23 % for ratio error and 0.29 min ${\sim}$ 1.93 min for phase displacement in the primary current ranges of 10 ${\sim}$ 40,000 A.

A Study on the Loop Current Induced by Voltage Phase Difference Substations during Parallel Feeding under the Alternating Current AT Electric Power Feeding Method (교류 AT급전방식에서 병렬급전시 변전소간 전압위상차에 의한 루프전류에 관한 연구)

  • Park, Jae-Seok;Song, Joong-Ho
    • Proceedings of the KSR Conference
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    • 2011.10a
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    • pp.1997-2004
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    • 2011
  • The $2{\times}25kv$ AT electric power feeding method in the A.C. electric train adopts the one-phase power feeding method as the standard due to a voltage phase difference, and the distance between the two neighboring substations is 50km due to voltage drop. The one-phase power feeding method makes the system operation feasible, while making it unfavorable for power supply. Moreover, railroad involves large-capacity single-phase load, and if it is expected to continue to rise, it is necessary to research on measures to stabilize the supply of power to railroad cars with the existing facilities. In this study, a parallel power feeding method between neighboring substations is proposed to stabilize the supply of electric power to electric railroad cars under the 2*25kv AT power feeding method and the loop current induced by voltage phase difference between the two neighboring substations during parallel power feeding is investigated.

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Sag & Swell Detection by Phase Voltage Compensation in 3-Phase Unbalanced Grid (3상 불평형 계통에서의 상 전압 보상을 통한 Sag 및 Swell 검출)

  • Kim, Min-Gi;Kim, Jun-Gu;Jung, Yong-Chae;Won, Chun-Yuen
    • Proceedings of the KIPE Conference
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    • 2013.11a
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    • pp.258-259
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    • 2013
  • Load connection or disconnection makes instantaneous sag & swell in 3-phase grid. When unbalance state occurs, between sensed phase voltage and actual phase voltage may have discrepancy. It makes difficult to detect accurate sag & swell, so it is hard to satisfy the standard for switching ESS system to UPS mode. In this paper, we analyzed unbalanced 3-phase voltage, and compensated the actual sag & swell magnitude.

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