• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.15-22
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• 1998

The goal of this paper is to propose analyzing and evaluating method of power parameters for motor drive system with various experimental graphic screens and numerical results and to develop the proposed system. A developed system is made up 586-PC and DSP board, motor drive system, power parameters analyzing and evaluating software for windows. Power parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis results are visualized by 3-D current coordinates, and it is compared and evaluated with conventional time/ frequency domain. To verify the validity of the proposed system, capacitor run type single phase induction motor and thyristor speed controller is used for analyzing. Power and harmonic parameters of motor drive system is analyzed and verified, with varying fire angle of thyristor speed controller, and the proposed approach is to confirm validity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1941-1948
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• 1997

In this paper, the power efficient linear upconversion mixer which is a functional circuit in transmit path of intermediate frequency(IF) part of Code Division Multiple (CDMA) cellular phone was explained. In generally, the low CMOS devices limits the implementation of upconversion mixer especially for lower loads. Using replica transconductor, the linear range is extended up to the limit. Thiscircuit was imprlemented using $0.8{\mu}\textrm{m}$ N-well CMOS technology with 2-poly/2-metal. The active area of chip is $0.53mm{\times}0.92mm$. The power consumption is 30mW with 3.3V suply voltage. The 1dB conpression characteristics is -27.3dB with $25{\Omega}$. load and being applied by 2-tone input signal. The mixer operates properly above 200MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1093-1098
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• 2007

Tilting trains are currently in operation in 13 countries around the world. With the advances in tilting technology, verification of economic efficiency, and changes in economic situations, the introduction of tilting trains will rapidly spread across the globe. The measurement system is composed of the industrial computers installed in the console and the measurement racks mounted on each car. It is utilized to accumulate the data by the communication card and the optical cable. The optical cable and power cable are coupled at the connector located in joint of train to make easy to disconnect car each other. The signal conditioner is designed to choose and to extend the channel for each sensor readily. The sensor measurement rack has adopted as decentralization method. It is installed in each car to minimize the cable length. In also, it is manufactured based on 19"rack and covered to protect the cable. In this study, the programs for measurement and analysis were also developed to understand the traction system characteristics of TTX. Using this measurement system, we studied that acceleration test, re-powering test, and gradually powering test. The acceleration performance of TTX is 1.735 km/h/s, and it is inner standard value. The notch test result from 1 to 7 steps, DC link voltage is under standard value, and the output electric current of inverter is controlled normally. From the test results, we saw the performances of the traction systems are normal.

• BMB Reports
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• v.28 no.6
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• pp.499-503
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• 1995

In our previous studies (Chae et al., 1990; Chae et a1., 1993), we found that a phytochrome signal was clearly connected with the change in cytosolic free $Ca^{2+}$ concentration ($[Ca^{2+}]_i$) in oat cells. It was determined that the $[Ca^{2+}]_i$ change occured both by mobilization out of the intracellular $Ca^{2+}$ store and by influx from the medium. The specific aim of this work is to elucidate the processes connecting $Ca^{2+}$ mobilization and influx. The cells treated with thapsigargin (increasing $[Ca^{2+}]_i$ by inhibition of the $Ca^{2+}$-ATPase in the calcium pool) in the presence of external $Ca^{2+}$ showed the same increasing pattern (sustained increasing shape) of $[Ca^{2+}]_i$ as that measured in animal cells. Red light irradiation after thapsigargin treatment did not increase $[Ca^{2+}]_i$ These results suggest that thapsigargin also acts specifically in the processes of mobilization and influx of $Ca^{2+}$ in oat cells. When the cells were treated with TEA ($K^+$ channel blocker), changes in $[Ca^{2+}]_i$ were drastically reduced in comparison with that measured in the absence of TEA. The results suggest that the change in $[Ca^{2+}]_i$ due to red light irradiation is somehow related with $K^+$ channel opening to change membrane potential. The membrane potential change due to $K^+$ influx might be the critical factor in opening a voltage-dependent calcium channel for $Ca^{2+}$ influx.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2010.11a
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• pp.590-593
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• 2010

The processes of supplying propellants into propellant tanks play important roles during launch preparation of satellite launch vehicle. The total weight of launch vehicle greatly depends on the accuracy of filling quantity of propellant during launch preparation. Among propellants used for launch vehicles a cryogenic propellant such as liquid oxygen is widely adapted as an oxidizer for launch vehicles. Such cryogenic propellant usually resides in a propellant tank as two-phase fluid with liquid and gas, which needs an accurate level measurement system to detect the position of propellant surface precisely. In this paper the fabricating process of a level measurement system using capacitance type with three electrodes is analyzed. In addition, the change of electric signal according to the height of liquid is verified by testing the level measurement system under consideration. The results of tests shows as expected the linear trend of voltage according to the change of water height in a tank.

• Journal of the Korean Magnetics Society
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• v.23 no.4
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• pp.135-143
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• 2013

The clip-type pulsimeter equipped with a Hall sensor has a permanent magnet attached in the "Chwan" position to the center of a radial artery. The clip-type pulsimeter is composed of a hardware system measuring voltage signals. These electrical bio-signals display pulse rate, non-invasive blood pressure, respiratory rate, pulse wave velocity (PWV), and spatial pulse wave velocity (SPWV) simultaneously measured by using the radial artery pulsimeter, the electrocardiograph (ECG), and the photoplethysmograph (PPG). The findings of this research may be useful for developing a oriental-western biomedical signal storage device, that is, the new and fusion patient monitor, for a U-health-care system.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.37-42
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• 2012

In this paper, a new charge pump is proposed to reduce the timing mismatch in the conventional current-steering charge pumps. Conventional current-steering charge pumps used NMOS input stages both for UP and DOWN signals, which resulted in different numbers of stage for UP and DOWN delay paths. The proposed charge pump has equalized the numbers of stages for UP and DOWN signals by using a PMOS stage for the DOWN signal. The simulation results show that the conventional current-steering charge pump has 14ns and 6ns for optimized timing mismatches between UP and DOWN signals for turn-on and turn-off, respectively. On the other hand, the proposed charge pump has improved timing mismatches of 6ns and 5ns for turn-on and turn-off, respectively. As a result, the reference spurs are reduced from -26dBc to -39dBc for the proposed charge pump. The proposed charge pump was designed by using $0.18{\mu}m$ CMOS technology. The measurement results show that the maximum variation of the charging and discharging current over the charge pump output voltage range of 0.3~1.5V is approximately 1.5%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.4
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• pp.41-46
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• 2012

This paper suggested that the frequency adaptive antenna matching network design between AP and WLAN(Wireless Local Area Network) terminal for improving performance. The internet data service of the WLAN terminal is communicated through the AP and AP broadcasts the beacon signal including the assigned frequency channel. at that time the antenna matching network path is controlled beacon information after the WLAN terminal searching and synchronization a beacon information. and then the WLAN terminal communicate with AP. controlling the antenna matching network path according to channel information, The WLAN terminal is expected to improve RF output power and sensitivity performance. The VSWR(Voltage Standing Wave Ratio) performance of the designed antenna matching network is measured to about 1.1 ~ 1.2 and then it is operated by the channel information of the AP.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.