• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.1-8
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• 2016

It is well known that the behavior of PV curves is similar to a quadratic function. This is used in some papers to approximate PV curves and calculate the maximum-loading point by minimum number of power flow runs. This paper also based on quadratic approximation of the PV curves is aimed at completing previous works so that the computational efforts are reduced and the accuracy is maintained. To do this, an iterative method based on a quadratic function with two constant coefficients, instead of the three ones, is used. This simplifies the calculation of the quadratic function. In each iteration, to prevent the calculations from diverging, the equations are solved on the assumption that voltage magnitude at a selected load bus is known and the loading factor is unknown instead. The voltage magnitude except in the first iteration is selected equal to the one at the nose point of the latest approximated PV curve. A method is presented to put the mentioned voltage in the first iteration as close as possible to the collapse point voltage. This reduces the number of iterations needed to determine the maximum-loading point. This method is tested on four IEEE test systems.

• Journal of Information Display
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• 제3권4호
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• pp.13-18
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• 2002

In general, the background light that is produced during the reset period deteriorates the dark room contrast ratio in AC PDP. In this paper, we propose a modified ramp reset pulse that can reduce the background light to an imperceptible level. In the new reset waveform, the discharges between the scan and sustain electrodes are minimized by applying a positive bias voltage to the sustain electrode and only the weak discharges between the scan and address electrodes are found to occur during the reset period. We also adopted the MgO coated phosphor layer to improve the address voltage margin that was reduced when the bias voltage in the modified ramp reset waveform was applied. As a result, the address voltage margin of 45 V which is the same level of the conventional method was ortained and the dark room contrast ratio was improved up to 7500 : 1.

• 대한전기학회논문지:전력기술부문A
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• 제52권10호
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• pp.557-562
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• 2003

This paper presents a power transfer capability calculation algorithm considering the closest saddle node bifurcation for voltage stability margin. In this method, voltage stability margin constraints considering the closest saddle node bifurcation are incorporated into a power transfer capability formulation to guarantee adequate voltage security levels in an interconnected power system. The proposed method is applied to IEEE-24 reliability test system and the results show the effectiveness of the method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전력기술부문
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• pp.88-90
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• 2002

This paper presents a power transfer capability calculation algorithm Considering A Closest Saddle Node Bifurcation For Voltage Stability Margin. In this method, voltage stability margin constraints considering a closest saddle node bifurcation are incorporated into a power transfer capability formulation to guarantee adequate voltage security levels in an interconnected Power System. The proposed method is applied to IEEE-24 Reliability Test System and the results shows the effectiveness of the method.

• KIEE International Transactions on Power Engineering
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• 제5A권2호
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• pp.144-151
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• 2005

This paper presents a framework for determining control strategies against unwanted tripping actions during relay operation that plays a very important role in cascading events leading to voltage collapse. The framework includes an algorithm for quick identification of possible zone 3 relay operation during voltage instability. Furthermore, it comes up with the control strategy of load shedding at the selected location with active power and relay margin criteria. In addition, Quasi Steady-State (QSS) simulation is employed to obtain time-related information that is valuable in the determination of control strategy. As a case study, an example applying the framework is shown with the modified New England 39-bus system.

• Transactions on Electrical and Electronic Materials
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• 제7권1호
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2386-2388
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• 1999

This paper describes the surface discharge characteristics which can be used as data to determine the optimumal length in margin which plays an important role in improving the energy density and the life-time of high voltage capacitors. In this experiment, the margin of metalized polypropylene films(MPPFs) is varied in length in order to measure and analyze flashover voltages and partial discharge inception voltages (PDIVS). As a result, the flashover voltage and the PDIV are increased with margin and tracking was observed.

• 에너지공학
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• 제7권1호
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• pp.65-72
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• 1998

이 논문은 극좌표이 선로조류방정식을 이용하여 전압안정성 여유전력을 평가하는 고속계산법을 제안한다. 여기서, 선로조류방정식은 상태변수 Vi, $\delta$i, Vj와 $\delta$i 그리고, 선로정수 r과 x로 구성되는데 극좌표계의 특징을 이용하면 이것은 두 개의 변수 Vi와 Vj를 가진 하나의 식이 된다. 그리고, j 모선이 조류계산에서 전압크기로 지정되는 발전기 또는 slack 모선이라면, 변수 Vi만을 가진 하나의 식 즉, {{{{ { V}`_{i } ^{2 } }}에 대한 2차 방정식으로 정식화된다. 그러므로, 전력조류다근은 간단한 계산을 통해 구할 수가 있는데 이와 같이 구해진 다근은 감도해석 또는 다근의 근접도를 통해 전압안정도를 평가할 수 가 있었다. 또한, 전압안정도 평가시에 중요한 요소인 전력용 콘덴서와 같은 조상설비를 고려하여 전압안정성 여유전력을 평가하는 방법을 개발하였다. 제안한 방법을 시험계통에 적용하여 유효성을 입증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.14-21
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• 2009

A digital differential transmitter based on CMOS inverter worked up to 2.8 Gbps at the supply voltage of 1 V with a $0.18{\mu}m$ CMOS process. By calibrating the output impedance of the transmitter, the impedance matching between the transmitter output and the transmission line is achieved. The PVT variations of pre-driver are compensated by the calibration of the rising-edge delay and falling-edge delay of the pre-driver outputs. The chip fabricated with a $0.18{\mu}m$ CMOS process, which uses the standard supply voltage of 1.8 V, gives the highest data rate of 4Gbps at the supply voltage of 1.2 V. The proposed calibration schemes improve the eye opening with the voltage margin by 200% and the timing margin by 30%, at 2.8 Gbps and 1 V.

• 전기학회논문지
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• 제58권6호
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• pp.1157-1165
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• 2009

In AC-PDP, it is necessary to achieve high luminance efficiency, high luminance and high definition by adopting technologies such as high xenon concentration, MgO doping, and long gap. However, it is very difficult to apply above technologies because they make the driving voltage margin reduced. Especially, high Xe concentration technology for high efficacy makes not only the driving voltage margin reduced but also the stability of reset discharge decreased at low temperature. In this paper, we studied temperature and voltage dependent stability of reset discharge and present the experimental results of the discharge characteristics at low temperature. In addition, we suggested the mechanism of bright noise and black noise at low temperature. Finally, we proposed double reset waveform to improve the bright noise and descending scan time method to improve the black noise.