• 전기학회논문지
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• 제56권12호
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• pp.2189-2195
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• 2007

In this paper, we propose a newly developed selective reset waveform of a ac PDP using the wide erase pulse technique with the control of address bias voltage. Although it is generally understood that the wide pulse erasing methode shows the narrow driving margin in an opposite discharge type ac PDP, we could obtain a moderate driving margin in a 3-electrode surface discharge type ac PDP. The obtained driving margin shows a strong dependency on the sustain voltage and the address bias voltage. The lower the sustain and the address bias voltage, the wider the driving margin. The pulse width of the proposed waveform is only $10{\mu}s$, which gives additional time to the sustain period, hence increases the brightness. The brightness and contrast ratio increase about 20% together comparing to the conventional ramp type selective reset waveform with the driving scheme of 10 subfield ADS method. The driving margin was measured with the line by line addressed pattern on the white test panel of 2inch diagonal size and the discharge gas was Ne+Xe4%, 400torr.

• 대한전기학회논문지:전력기술부문A
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• 제55권12호
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• pp.536-543
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• 2006

This paper uses Monte Carlo technique, which is one of probabilistic methods of estimating the economical quantity of electric power generation in consideration of voltage stability in the aspect of power generation companies. In the power exchange system in Korea, when power generation companies participate in tenders for power generation capacity at the power exchange, they need to determine their power supply capacity considering the stability of electric power system. Thus, we purposed to propose an algorithm for estimating economical power generation capacity in theaspect of power generation companies, through which we can estimate the margin for voltage stability through P-V curve analysis by capacity according to the change of power generation capacity in a simulated system and to conduct Monte Carlo simulation in consideration of the margin

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 A
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• pp.19-23
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• 2003

This paper presents a new concept of reactive reserve based contingency constrained optimal power flow (RCCOPF) for voltage stability enhancement. This concept is based on the fact that increase in reactive reserves is effective for enhancement of voltage stability margins of post-contingent states, in this paper, the proposed algorithm is applied to voltage stability margin of interface flow. Interface flow limit, in the open access environment, can be a main drawback. RCCOPF for enhancement of interface flow margin is composed of two modules, modified continuation power flow (MCPF) and optimal power flow (OPF). These modules art recursively perform ed until satisfying the required margin of interface flow in the given voltage stability criteria.

• 조명전기설비학회논문지
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• 제17권3호
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• pp.18-24
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• 2003

전력산업구조 개편 시 변화된 전력계통 환경하에서 효율적인 계통운용 및 계획을 위해서는 계통의 수송능력(Power Transfer Capability)을 산정하는 작업이 필수적이다. 또한 송전망의 자유로운 접근(Open Access)과 같은 전력정책의 변화로 인하여 전력계통은 더욱더 고부하상태에서 운전될 가능성이 높아지게 되었다. 전력계통의 부하가 증가하면 전압안정도 여유가 감소하므로 전력계통은 전압붕괴와 같은 전압안정도 문제를 야기시킬 수 있다. 본 연구에서는 전력계통의 수송능력 산정문제에 대해 전압안정도여유 제약을 고려 할 수 있는 수송능력산정 알고리즘 개발에 연구의 목적을 두고 있다. 이를 위해 본 연구에서는 전압안정도 여유제약식을 정식화한 다음 이를 수송능력 산정문제에 반영할 수 있는 방법을 제안하였다. 그리고 이를 시험계통에 적용하여 본 연구의 타당성을 검증하고 유응한 정보를 도출하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.685-694
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• 2015

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.77-80
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• 2000

This paper describes a new method to decide the margin for the sustain voltage of AC PDPs based on the wall-charge distribution. We model the discharge cell and measure the wall-charge when sustain pulses are applied to the AC PDP. The measured wall-charge distribution informs us of the voltage forming the maximum wall-charge which should be chosen as the sustain voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 A
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• pp.19-21
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• 2002

This paper presents a power transfer capability calculation algorithm Considering Voltage Stability Margin. In this method, voltage stability margin constraints are incorporated into a power transfer capability formulation to guarantee adequate voltage security levels in interconnected Power System. The proposed method is applied to IEEE-24 Reliability Test Systems and the results shows the effectiveness of the method.

• 대한전기학회논문지:전력기술부문A
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• 제54권6호
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• pp.274-283
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• 2005

This paper presents a new method to derive energy function based on vector product. Using this method, an energy function to consider transfer conductances and capacitors is derived. Then we recommend a voltage collapse criteria to predict the voltage collapse in power systems by using the energy margin derived by the proposed energy function. This energy function is applied to a 2-bus power system reflecting transfer conductances and capacitors. We show that the energy function derived based on vector product can be applied in order to analyze power system stability and the energy margin can be utilized as a criterion of voltage collapse by simulation for the 2-bus system.

• 전기학회논문지
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• 제56권11호
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• pp.2004-2009
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• 2007

A new high-speed drive method for the plasma display panel is proposed. In this method, the address period is inserted for the rest period of the sustain pulses and the priming pulse is applied on the entire panel at the same time overlapping with the sustain period. The ramp shaped priming pulse can be made with a simple drive circuit in this technology and the stable sustain discharge can be induced even by a narrow scan pulse in help of the space charge generated from the address discharge. From the experiments, it is ascertained that the priming pulse hardly influences the sustain discharge. Moreover, the voltage margin of the sustain discharge is almost constant though that of the address discharge broadens with narrowing the scan pulse width. And, if the time interval between the scan pulse and the sustain pulse is within $6{\mu}s$, the voltage margin of the address and the sustain discharges are unaffected though the applied position of the scan pulse is changed. High-speed driving with the address pulse of $0.7{\mu}s$ width was achieved and the address voltage margin of 20V and the sustain voltage margin of 10V were obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.103-104
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• 2000

Voltage transfer curves have been used for analyzing the micro-discharge characteristics of cells in ac-PDP. This paper deals with the effect of working gas species, pressure and frequency of applied voltage on the micro-discharge characteristics. Using the mixture gases of He+Xe or He+Ne+Xe, wall voltage steeply varied compared with only He gas, and also voltage margin increased. Discharge voltage and voltage margin increased with increasing Xe percentage, and also wall voltage more steeply varied. In addition, the variation of effective wall capacitance which is significantly dependent on the discharge strength is discussed.