• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2747-2753
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• 2011

In this paper, a PWM current-mode DC-DC boost converter for mobile phone flash application has been proposed. The converter which is operated with 5 Mhz high switching frequency is capable of reducing mounting area of passive devices such as inductor and capacitor, consequently is suitable for compact mobile phones. This boost converter consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. Meanwhile, the control block consists of pulse width modulator, error amplifier, oscillator etc. Proposed boost converter has been designed and verified in a $0.5\;{\mu}m$ 1-poly 2-metal CMOS process technology. Simulation results show that the output voltage is 4.26 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 Khz driven converter when the duty ratio is 0.15.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.819-825
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• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.1
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• pp.84-90
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• 2010

In this paper, a novel voltage-controlled oscillator (VCO) using the harmonic control circuit based on the composite right/left-handed (CRLH) transmission lines (TLs) is presented to reduce the phase noise without the reduction of the frequency tuning range and miniaturize the circuit size. The phase noise is reduced by the novel harmonic control circuit having the short impedances for the second- and third-harmonic components. The proposed harmonic control circuit is designed by using the CRLH TLs with the dual-band characteristic by the frequency offset and phase slope of the CRLH TLs. The high-Q resonator has been used to reduce the phase noise, but has the problem of the frequency tuning range reduction. However, the frequency tuning range of the proposed VCO has not been reduced because the phase noise has been reduced without the high-Q resonator. The miniaturization of the circuit size is achieved by using the CRLH TLs instead of the conventional right-handed (RH) TLs. The phase noise of VCO is -119.17 ~ -117.50 dBc/Hz at 100 kHz in the tuning range of 5.731 ~ 5.938 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.8-15
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• 2002

We optimally designed the VCO(voltage-controlled oscillator) with spiral inductor using the MOSIS HP 0.5${\mu}{\textrm}{m}$ CMOS process. With the developed SPICE model of spiral inductor, the quality factor of spiral inductor was maximized at the operating frequency by varying the layout parameters, e.g., metal width, number of turns, radius, space of the metal lines. For the operation frequency of 2㎓, the inductance of about 3nH, and the MOSIS HP 0.5 CMOS process with the metal thickness of 0.8${\mu}{\textrm}{m}$, oxide thickness of 3${\mu}{\textrm}{m}$, the optimal width of metal lines is about 20${\mu}{\textrm}{m}$ for the maximum Quality factor. With the optimized spiral inductor, the VCO with LC tuning tank was designed, fabricated and measured. The measurements were peformed on-wafer using the HP8593E spectrum analyzer. The oscillation frequency was about 1.610Hz, the frequency variation of 250MHz(15%) with control voltage of 0V - 2V, and the phase noise of -108.4㏈c(@600KHz) from output spectrum.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.35-40
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• 2005

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using the 3rd order ${\Delta}{\sum}$ modulator for 900MHz medium speed wireless link. The LC voltage-controlled oscillator (VCO) is used for the good phase noise property. To reduce the lock-in time, a charge pump has been developed to control the pumping current according to the frequency steps and the reference frequency is increased up to 3MHz. A 36/37 fractional-N divider is used to increase the reference frequency of the phase frequency detector (PFD) and to reduce the minimum frequency step simultaneously. A 3rd order ${\Delta}{\sum}$ modulator has been developed to reduce the fractional spur VCO, Divider by 8 Prescaler, PFD and Charge pump have been developed with 0.25um CMOS, and the fractional-N divider and the third order ${\Delta}{\sum}$ modulator have been designed with the VHDL code, and they are implemented through the FPGA board of the Xilinx Spartan2E. The measured results show that the output power of the PLL is about -lldBm and the phase noise is -77.75dBc/Hz at 100kHz offset frequency. The minimum frequency step and the maximum lock-in time are 10kHz and around 800us for the maximum frequency change of 10MHz, respectively.

• Resources Recycling
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• v.29 no.1
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• pp.25-34
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• 2020

Electrochemical Quartz Crystal microbalance is a tool that is capable of measuring nanogram-scale mass change on electrode surface. When applying alternating voltage to the quartz crystal with metal electrode formed on both sides, a resonant frequency by inverse piezoelectric effect depends on its thickness. The resonant frequency changes sensitively by mass change on its electrode surface; frequency increase with metal dissolution and decrease with metal deposition on the electrode surface. The relationship between resonant frequency and mass change is shown by Sauerbrey equation so that the mass change during metal dissolution can be measured in real time. Especially, it is effective in the case of reaction mechanism and rate studies accompanied by precipitation, volatilization, compound formation, etc. resulting in difficulties on ex-situ AA or ICP analysis. However, it should be carefully considered during EQCM experiments that temperature, viscosity, and hydraulic pressure of solution, and stress and surface roughness can affect on the resonant frequency. Application of EQCM was shown as a case study on leaching of platinum using aqueous chlorine for obtaining activation energy. A platinum electrode of quartz crystal oscillator with 1000 Å thickness exposed to solution was used as leaching sample. Electrogenerated chlorine as oxidant was purged and its concentration was controlled in hydrochloric acid solution. From the experimental results, platinum dissolution by chlorine is chemical reaction control with activation energy of 83.5 kJ/mol.