• Title/Summary/Keyword: vision chip

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A Real-Time Virtual Re-Convergence Hardware Platform

  • Kim, Jae-Gon;Kim, Jong-Hak;Ham, Hun-Ho;Kim, Jueng-Hun;Park, Chan-Oh;Park, Soon-Suk;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.127-138
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    • 2012
  • In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

Development of a LonRF Intelligent Device-based Ubiquitous Home Network Testbed (LonRF 지능형 디바이스 기반의 유비쿼터스 홈네트워크 테스트베드 개발)

  • 이병복;박애순;김대식;노광현
    • Journal of Institute of Control, Robotics and Systems
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    • v.10 no.6
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    • pp.566-573
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    • 2004
  • This paper describes the ubiquitous home network (uHome-net) testbed and LonRF intelligent devices based on LonWorks technology. These devices consist of Neuron Chip, RF transceiver, sensor, and other peripheral components. Using LonRF devices, a home control network can be simplified and most devices can be operated on LonWorks control network. Also, Indoor Positioning System (IPS) that can serve various location based services was implemented in uHome-net. Smart Badge of IPS, that is a special LonRF device, can measure the 3D location of objects in the indoor environment. In the uHome-net testbed, remote control service, cooking help service, wireless remote metering service, baby monitoring service and security & fire prevention service were realized. This research shows the vision of the ubiquitous home network that will be emerged in the near future.

Developement of IC Mark Checking System for IC Inspection Automation (반도체 소자(IC)의 검사 자동화를 위한 IC 표면의 마크 검사시스템 개발)

  • Bien, Zeung-Nam;You, Bum-Jae;Han, Dong-Il;Oh, Sang-Rok;Kim, Jung-Duck;Ha, Kyung-Ho
    • Proceedings of the KIEE Conference
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    • 1990.07a
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    • pp.471-474
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    • 1990
  • In this paper, a vision-based inspection algorithm for checking mark quality on an integrated chip(IC) is proposed. In order to reduce the processing time for inspection, we are implemented image arithmetic unit and binary image projection processor in hardware. By adopting the hardwares, the processing time becomes less one sixth of that in case of using software only.

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Comparison of Driving Time between Stop-motion Method and Moving-motion Method

  • Kim, Soon-Ho;Kim, Chi-Su
    • Journal of Advanced Information Technology and Convergence
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    • v.8 no.2
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    • pp.139-145
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    • 2018
  • Improvement of the speed of the gantry among equipment that mounts a chip using SMT can improve productivity. In order to improve the performance of the gantry, there are studies such as a method of increasing the speed of adsorption, the speed of the gantry by reducing the weight, and a method of facilitating the use of the gantry. But all of these are ways of improving equipment. In this paper, we propose a method to improve the speed of gantry mounting microchip. The method is to shorten the driving time of the gantry. To do this, calculate the driving time using the existing method. And we calculate the travel time using the method presented in this paper. As a result, the time calculated by the proposed method is reduced by 14%.

The Method to Reduce the Driving Time in (sLa-Camera-pRd) type ((sLa-Camera-pRd)타입의 구동시간 단축 방법)

  • Kim, Soon-Ho;Kim, Chi-Su
    • Journal of the Korea Convergence Society
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    • v.9 no.12
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    • pp.1-7
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    • 2018
  • Gentry is responsible for moving the fine chip in the device that mounts the chip on the PCB. However, it is not easy to increase productivity because of the mechanical limitations of the gantry. Therefore, in this paper, we try to solve the method to increase the productivity by software. For this purpose, we propose a method to improve the productivity by shortening the movement time of the gantry. First, we calculated the total travel time for the current method(stop-motion). In addition, the total travel time is also calculated for the travel time reduction method presented in this paper. This method reduces the travel time by checking parts without stopping in front of the camera. As a result, we showed that the proposed method shortened the time of 16%. In the future, we will study time calculation methods for other types.

Emphasizing Intelligent Event Processing Cooperative Surveillance System (지능형 사건 처리를 강조한 협업 감시 시스템)

  • Yoon, Tae-Ho;Song, Yoo-Seoung
    • IEMEK Journal of Embedded Systems and Applications
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    • v.7 no.6
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    • pp.339-343
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    • 2012
  • Security and monitoring system has many applications and commonly used for detection, warning, alarm, etc. As the networking technology advances, user requirements are getting higher. An intelligent and cooperative surveillance system is proposed to meet current user demands and improve the performance. This paper focuses on the implementation issue for the embedded intelligent surveillance system. To cover wide area cooperative function is implemented and connected by wireless sensor network technology. Also to improve the performance lots of sensors are employed into the surveillance system to reduce the error but improve the detection probability. The proposed surveillance system is composed of vision sensor (camera), mic array sensor, PIR sensor, etc. Between the sensors, data is transferred by IEEE 802.11s or Zigbee protocol. We deployed a private network for the sensors and multiple gateways for better data throughput. The developed system is targeted to the traffic accident detection and alarm. However, its application can be easily changed to others by just changing software algorithm in a DSP chip.

An Embedded FPGA Implementation for a Cameralink Interface (카메라링크 접속을 위한 임베디드 FPGA의 구현)

  • Lee, Chang-Su
    • Journal of IKEEE
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    • v.15 no.2
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    • pp.122-128
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    • 2011
  • Although conventional analog linescan cameras are used widely, high-speed, high-resolution Cameralink standard will lead the area of frame grabber industry such as factory automation. In this paper, we are developing embedded frame grabber testbed without PC which will give an another solution to image processing applications. Therefore, we designed hardware schematics and programmed FPGA device with VHDL in order to interface Cameralink standard linescan CCD camera. In the future, our embedded on-chip controller could be applied to various image processing systems such as medical imaging, especially optical coherence tomography, machine vision and industrial electronics.

Design and Implementation of Content Switching Network Processor and Scalable Switch Fabric

  • Chang, You-Sung;Yi, Ju-Hwan;Oh, Hun-Seung;Lee, Seung-Wang;Kang, Moo-Kyung;Chun, Jung-Bum;Lee, Jun-Hee;Kim, Jin-Seok;Kim, Sang-Ho;Jung, Hee-Jae;Hong, Il-Sung;Kim, Yong-Hwan;Lee, Yu-Sik;Kyung, Chong-Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.167-174
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    • 2003
  • This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.

Implementation of an FPGA-based Frame Grabber System for PCB Pattern Detection (PCB 패턴 검출을 위한 FPGA 기반 프레임 그래버 시스템 구현)

  • Moon, Cheol-Hong
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.2
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    • pp.435-442
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    • 2018
  • This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.

Development of a Robotic Milking Cluster System (착유 자동화를 위한 로봇 착탈 시스템)

  • 이대원;최동윤;김현태;이원희;권두중;이승기;한정대
    • Journal of Animal Environmental Science
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    • v.6 no.2
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    • pp.113-119
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    • 2000
  • A Robotic milking cluster system with the manipulator for an automatic milking system was designed and built for farmer to work easily and comfortably during milking processing. The cluster system was composed of screws, cams and links for power transmission, DC motors, the Quick Basic one-chip microprocessor, the vision system for image processing, and tea-cups. Software, written in Visual C+ and Quick Basic, combined the function of image capture, image processing, milking cluster control, and control into one control. The unit was made to transfer from four fixed points to four teats with four teat-cups. Performance tests of the cluster unit, the fully integrated system, were conducted to attach and detach the teat-cup on the teat of a artificial cow. The transfer programming provided for a teat-cup milking loop during the system starts and comes back the original fixed point at the manipulator of it for milking. It transferred the teat-cup with a success rate of more than 70%. The average time it took ot perform the milking loop was about 20 seconds.

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