• Journal of IKEEE
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• v.27 no.3
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• pp.234-238
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• 2023

In this paper, we propose a time-to-digital converter (TDC) with compensation capability for PVT (process, voltage, and temperature) variations. A typical delay line-based TDC measures time based on the inverter's propagation delay, making it fundamentally sensitive to PVT variations. This paper presents a method to minimize the resolution change of TDC by compensating for the propagation delay caused by the PVT variations. Additionally, it dopts Cyclic Vernier TDC (CVTDC) structure to provide a wide input detection range. The proposed CVTDC with PVT compensation function is designed using a 45nm CMOS process, consumes 8mW of power, offers a TDC resolution of 5 ps, and has an input detection range of about 5.1 ns.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.721-725
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• 1996

The microfabricated test structures were used in order to evaluate the stress characteristics in films. The test structures were fabricated using surface micromachining technique, including HF vapor phase etching as an effective release method. The fabricated structures were micro strain gauge, cantilever-type vernier gauge and bridge for stress measurement, and cantilever for stress gradient measurement. The strain was measures by observing the deformation of the structures occurred after release etching and the amount of deformation can be detected by micro vernier gauge, which has gauge resolution of 0.2${\mu}{\textrm}{m}$. The detection principles and the degree of precision for the measured strain were also discussed. The characteristics of residual stress in LPCVD polysilicon films were studied using these test structures. The stress gradient due to the stress variation through the film thickness was calculated by measuring the deflection at the cantilever free end.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.334-341
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• 2015

This research outlines the design of a HR-TDC (High Resolution Time-to-Digital Converter) for high data rate communication systems using a $0.18{\mu}m$ CMOS process. The coarse-fine architecture has been adopted to improve the resolution of the TDC. A two-stage vernier time amplifier (2S-VTA) was used to amplify the time residue, and the gain of the 2S-VTA was larger than 64. The error during time amplification was compensated using two FTDCs (Fine-TDC) with their outputs. The resolution of the HR-TDC was 0.15 ps with a 12-bit output and the power consumption was 4.32 mW with a 1.8-V supply voltage.

• Proceedings of the Optical Society of Korea Conference
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• 1999.08a
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• pp.126-127
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• 1999

• Journal of Korean Ophthalmic Optics Society
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• v.14 no.4
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• pp.77-81
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• 2009

Purpose: To study the change of fixation disparity and accommodation as fusion contrast is deteriorated. Methods: 16 subjects who had above 20/20 and stereopsis took part. Monocular and binocular refraction were done with Zeiss Polatest Classic whereas the critical angle for stereopsis was done with TNO. A computer programmed with Random-Dot stereogram and vernier test managed a precise change of the fusion contrast and exposure time. Results: The fixation disparity was influenced by reduction of fusion contrast and had tendancy to exophoria (p=0.0004), especially it is considerably higher when uncrossed disparity was shown to exophoric subjects. Although accommodation was not influenced by a change of fusion contrast (p=0.803), vernier acuity was influenced (p=0.0000). Conclusions: Exophoric trend arose as the fusion contrast was reduced, nevertheless there was no accommadative change.

• Korean Journal of Optics and Photonics
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• v.11 no.4
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• pp.232-238
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• 2000

The new collimation testing technique of a white light beam using vernier Moire fringes of two line or circular gratings with different pitches is presented. We can visually measure the defocusing ($\Deltaf$), the divergence angle ($\theta$), and the longitudinal chromatic aberration $(L_{ch})$ of a collimating lens by using the technique. For example, we obtained $\Deltaf$= 21.9 mm and $\theta=0.0038^{\circ}$ for a testing lens with the focallengthf = 120.0 mm and F-number of F/2.4. The longitudinal chromatic aberration $L_{ch}$ of another testing lens withf = 65.0 mm, F/1.6, and the Abbe number V = 64.1 for the incident wavelengths of $\lambda_1=480 nm and \lambda_2=640 nm$ is easily measured by same technique. It is found that the measured value $L_{ch}=1.59mm(\pm0.01mm)$ is well agreed with $L_{ch}=1.58mm(\pm0.01mm)$ obtained by the autofocus method.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.21-29
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• 2002

This paper describes a high resolution DLL(Delay Locked Loop) using all digital circuits. The proposed architecture is based on the three stage of coarse, fine and ultra fine phase tuning block which has a phase detector, selection block and delay line respectively. The first stage, the ultra fine phase tuning block, is tune to accomplish high resolution using a vernier delay line. The second and third stage, the coarse and fine tuning block, are tuning the phase margin of Unit Delay using the delay line and are similar to each other. It was simulated in 0.35um CMOS technology under 3.3V supply using HSPICE simulator. The simulation result shows the phase resolution can be down to lops with the operating range of 250MHz to 800MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.7-13
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• 2011

This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

• Proceedings of the Optical Society of Korea Conference
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• 2006.02a
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• pp.313-314
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• 2006

We have investigated the wavelength tuning characteristics due to the vernier effect of coupled-ring reflector laser diode including active region within resonators using time-domain modeling. It is shown that the wavelength can be widely tuned with side mode suppression ratio more than 30dB by adjusting the refractive index difference between mismatched rings.

• Journal of Dental Rehabilitation and Applied Science
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• v.24 no.1
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• pp.77-89
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• 2008

The purpose of this study was to evaluate internal conical abutment sinking and fitness according to the loading condition. In this study, Alloden implant fixture and two abutment(conventional, FDI) systems were used. Each abutment was applied 1 time of finger force, 3 times of malleting force, 5 times of 20kg and extra several times to the fixture until the amount of abutment singking showed no change. Then, the length of abutment to fixture which was binding lightly with no pressure state was measured by Vernier caliper. After loading application, the length was remeasured and the amount of sinking was calculated. The implant was buried in unsaturated polyester (Epovia, Cray Valley Inc. Korea) for making a comparison between the change of length and fitness of abutment-fixture connection part. Then All samples were cross-sectioned with high speed precision cut-off(accutom-5, Struers, Denmark). Finally, The result were observed and analyzed using FE-SEM (field emission scanning electron microscopy).