• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.1-8
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• 2017

Lightweight Encryption Algorithm(LEA) was developed by National Security Research Institute(NSRI) in 2013 and targeted to be suitable for environments for big data processing, cloud service, and mobile. LEA specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, block cipher LEA algorithm which can encrypt and decrypt 128-bit messages is designed using Verilog-HDL. The designed IP for encryption and decryption has a maximum throughput of 874Mbps in 128-bit key mode and that of 749Mbps in 192 and 656Mbps in 256-bit key modes on Xilinx Vertex5. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.37-43
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• 2009

The new still image compression standard JPEG2000 is consisted of DWT and EBCOT. In this paper, proposed and designed new algorithm in efficient EBCOT. BPC based on the contort. Proposed BPC Algorithm is forecasted coding pass using Sigstage, column, mpass value. BAC design apply 4-pipeline stage. EBCOT designed using Verilog HDL. Verification and Synthesis using Xillinx FPGA technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.777-784
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• 2004

In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.49-54
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• 2005

This paper proposes the low power MDCT algorithm for precise FV with minimum size of sub-window in mobile phone. Proposed algerian uses the coefficient at the middle of whole result process requiring the least number of calculations, since it has a good characteristic when used as standard of the FV and needs minimum amount of operation. In addition, using the DCT result related to the middle frequency makes the characteristic of FV more superior because it suppresses the impulsive noise and difference of focus values is larger than any others. The proposed algorithm is implemented using Verilog HDL and verified using Excalibur-ARM board.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.138-144
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• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1387-1394
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• 2011

In this paper, a low-area symbol timing offset synchronization structure for WLAN Modem is proposed. Using CSD(Canonic Signed Digit) coefficients and CSS(Common Sub-expression Sharing) technique for the filter implementation, efficient structure for multiplication block can be obtained. Function simulation for proposed structure is done by using the preamble with timing offset. Through Verilog-HDL coding and synthesis, it is shown that the proposed symbol timing offset synchronization structure can be implemented with low-area semiconductor.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.59-62
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• 2003

The purpose of this paper is to present how to implement Segment_LCD display using SoC design. The SoC design is achieved by using an ARM_based Excalibur device. The Excalibur device offers an outstanding embedded development platform with ARM922T and FPA. The design in the Excailbur device uses the embedded AR띤 Processor core and the AMBA high-performance bus (AHH) to write to a memory-mapped slave peripheral in the FPGA portion of the device. Here, Segment_LCD is one kind of memory-mapped slave peripherals. In order to Implement the Segment_LCD display based on SoC design, four steps are fellowed. At first, IP modules are made by using Verilog HDL. Secondly, the ARM processor of the Excalibur is programmed using C in ADS (ARM Developer Suite). And in the third step, the whole system is simulated and verified. At last, modules are downloaded to SoCMaster kit. Both Quartus II software and ModelSim5.5e software are the key software tools during the design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.7
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• pp.1581-1588
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• 2010

Most digital cameras use a single image sensor with Color Filter Array(CFA) for the advantage of costs and speed. The various color interpolation(demosaicing) algorithms are researched to reconstruct a full representation of the image. In this paper, we proposed a method of demosaicing about using weighted directional filter for vertical, horizontal, and diagonal direction edge. The method considered the efficiency of hardware resources for hardware implementation. The performance of proposed method was confirmed by comparing the conventional method in experiments using 24 Kodak test images. The proposed method was designed by Verilog HDL and was verified by using Virtex4 FPGA boards and CMOS Image Sensor.