• 태양에너지
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• 제9권1호
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• pp.62-69
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• 1989

This analysis is to investigate the influence of inflow angle when cooling air flows into PC (Printed Circuit) board channels. Flow between PC board channels with heat generating blocks is assumed laminar, incompressible, two-dimensional. Geometric parameters (block spacing (S), block height (H), block width (W) and channel height (L)) are held fixed. Inflow angle variations are $-10^{\circ},\;0^{\circ},\;10^{\circ}$, where uniform heat flux per unit axial length Q (W/m) from heated block surfaces is generated. The governing equations for velocity and temperature are solved by SIMPLE (Semi-Implicit Method Pressure for Linked Equation) algorithm. Nusselt number on each block surfaces is analyzed after a numerical calculation result. The result shows that the assumption on parallel inflow (inflow angle to channel, $0^{\circ}$) to PC board channels can be used without large error even when inflow' angle is varied.

• 전기학회논문지
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• 제68권1호
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.366-370
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• 2003

This paper introduces a new design and fabrication technology of 28 GHz low-cost up and down converter modules for digital microwave radios, The design of the converter module is based on unit circuit blocks, which are to be characterized using a special test fixture. Based on the cascade analysis of the module the 28 GHz up and down converter modules have been designed and implemented. The measured module performance agrees with the cascade analysis. New components such as a tapped edge-coupled filter and a new Ka-band waveguide-to-microstrip transition, which are less sensitive to fabrication tolerances, have been used in the module implementation.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1005-1014
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• 1990

This paper proposes the control unit of a 32-bit high-performance RISC type microprocessor. This control unit controls the whole data path of target processor and on chip instruction/data caches in 4-stage pipelined scheme. For the improvement of speed, large parts of data path and control unit are designed by domino-CMOS and hard-wired circuit technology. First, in this paper, target processor's instruction set and data path are defined, and next, all signals needed to control the data path are analyzed. The decoder of control unit and clock generated logic block are implemented in DCAL(Dynamic CMOS Array Logic) with modified clock scheme for the purpose of speed up and supporting RISC processor's pipelined architecture efficiently.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 유공압시스템학회논문집
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• 제6권1호
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• pp.10-16
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• 2009

Automatic power transmission systems consisted of a torque converter and several planetary gear sets, clutches and brakes are controlled by a hydraulic shift control circuit and an electronic transmission control unit. The hydraulic circuit serves for the operation of the torque converter and lubrication oil supply of the transmission system as well as for the actuation of clutches for the automatic gear shift. The complicated hydraulic control circuit constructed by many spools, solenoids, orifices and flow passages are integrated into one small valve block and it is powered by one hydraulic pump. In this paper, a test equipment was developed to measure the oil consumption of each component at various wide operating conditions. Test data about 730 sets acquired from five test items are analyzed and discussed on the oil capacity of the circuit.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.581-584
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• 2014

본 논문에서는 에너지 분배 기능을 이용하여 MPPT(Maximum Power Point Tracking) 제어 기능을 구현한 마이크로 빛에너지 하베스팅 시스템을 제안한다. 소형 PV(Photovoltaic) 셀에서 출력되는 에너지와 전압 레벨은 작기 때문에 직접 MPPT 제어회로를 구동하기 어렵다. 따라서 제안된 회로에서는 시동회로를 사용하여 Vcp를 MPPT 제어회로를 구동하기 위해 필요한 전압까지 승압시킨다. Vcp가 원하는 전압 값에 도달하면 전압감지기가 이를 감지하여 PV 셀로부터 시동회로에 공급되는 에너지는 차단하고, 전력변환기에 에너지를 공급한다. Vcp가 감소하여 MPPT 제어회로가 동작하기 어렵게 되면 전력변환기로의 에너지 전달을 차단하고 시동회로를 다시 구동한다. 이렇게 에너지 분배 기능을 이용하여 시동회로와 전력변환기를 번갈아 동작시키면서 에너지를 수확하여 PMU(Power Management Unit)를 통해 부하에 전달한다. 제안된 회로는 0.35um CMOS 공정으로 설계 되었으며 모의실험을 통해 동작을 검증하였다. 설계된 회로의 칩 면적은 패드를 포함하여 $1430um{\times}1110um$이다.

• 전기전자학회논문지
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• 제9권1호
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• pp.1-6
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• 2005

본 논문에서는 CMOS 다치 논리회로를 이용한 고성능 곱셈기를 제안하였다. 이 곱셈기는 Modified Baugh-Wooley 곱셈 알고리즘과 전류모드 4치 논리회로를 적용하여 트랜지스터의 수를 감소시키고 이에 따른 상호연결 복잡도를 감소시켜 곱셈기 성능을 향상시켰다. 제안한 회로는 전압모드 2진 논리신호를 전류모드 4치 논리신호로 확장하는 동시에 부분 곱을 생성하고 4치 논리 가산기를 통해 가산을 수행 후 전류모드 4치-2진 논리 변환 디코더를 이용하여 출력을 생성한다. 이와 같이 곱셈기의 내부는 전류모드 4치 논리로 구성하였으며 입출력단은 전압모드 2진 논리회로의 입,출력을 사용함으로써 기존의 시스템과 완벽한 호환성을 갖도록 설계하였다. 이 곱셈기는 6.1mW의 소비전력과 4.5ns의 전달지연을 보였으며, 트랜지스터 수는 두 개의 비교 대상 회로에 비해 60%, 43% 노드 수는 46%, 35% 감소하였다. 설계한 회로는 3.3V의 공급전원과 단위전류 5uA를 사용하여, 0.35um 표준 CMOS 공정을 이용하여 구현하였으며, HSPICE를 사용하여 그 타당성을 입증하였다.

• Journal of Power Electronics
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• 제16권2호
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• pp.786-797
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• 2016

This paper describes the design and development of a novel semiconductor-based solid-state switch for damped oscillating voltage test system. The proposed switch is configured as two identical series-connected switch stacks, each of which comprising 10 series-connected IGBT function units. Each unit consists of one IGBT, a gate driver, and an auxiliary voltage sharing circuit. A single switch stack can block 20 kV-rated high voltage, and two stacks in series are proven applicable to 30 kV-rated high voltage. The turn-on speed of the switch is approximately 250 ns. A flyback topology-based power supply system with a front-end power factor correction is built for the drive circuit by loosely inductively coupling each unit with a ferrite core to the primary side of a power generator to obtain the advantages of galvanic isolation and compact size. After the simulation, measurement, and estimation of the parasitic effect on the gate driver, a prototype is assembled and tested under different operating regimes. Experimental results are presented to demonstrate the performance of the developed prototype.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.415-418
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• 2011

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low-density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. 최소합(min-sum) 복호 알고리듬 기반의 DFU는 2의 보수 값과 sign-magnitude 값 사이의 변환이 필요하여 회로가 복잡해진다. 본 논문에서는 sign-magnitude 연산 기반의 DFU를 설계하여 수체계 변환과정을 제거함으로써 회로를 간소화시키고 동작속도를 향상시켰다.