• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.319-325
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• 2015

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in $0.18{\mu}m$ CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

• 전자공학회논문지
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• 제53권7호
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• pp.131-137
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• 2016

본 논문에서는 기존의 2D IC의 성능을 개선하고 3D IC의 집적도와 전기적인 특성을 개선하기 위한 목적으로 연구되고 있는 TSV (Through Silicon Via)의 임피던스를 해석하였다. 향후 Full-chip 3D IC 시스템 설계에서 TSV는 매우 중요한 기술이며, 높은 집적도와 광대역폭 시스템 설계를 위해서 TSV에 대한 전기적인 특성에 관한 연구가 매우 중요하다. 따라서 본 연구에서는 Full-chip 3D IC를 설계하기 위한 목적으로 다중 TSV-to-TSV에서 거리와 주파수에 따른 TSV의 임피던스 영향을 해석하였다. 또한 이 연구 결과는 Full-chip 3D IC를 제조하기 위한 반도체 공정과 설계 툴에 적용할 수 있다.

• 한국재료학회지
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• 제5권8호
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• pp.929-935
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• 1995

구동 IC를 유리기판 위의 Al패드 전극에 연결하는 LCD(Liquid Crystal Display) 모듈을 실장하는 Chip On Glass (COG) 기술을 개발하기 위하여 기존에 잘 알려진 기술 가운데 실제로 적용 가능성이 가장 유망한 이방성 도전 접착제 (ACA, Anisotropic Conductive Adhesives)를 사용한 공정에 대하여 조사하였다. ACA 공정은 본딩 부분에 ACA 수지를 균일하게 분포시키는 공정과 자외선을 조사하여 수지를 경화하여 칩을 실장하는 공정의 2단계로 진행하였다. 칩에 가해준 하중은 2-15kg이었고 칩의 예열 온도는 12$0^{\circ}C$이었다. 이방성 도전체는 Au 또는 Ni이 표면 피막 재료로 사용된 것을 사웅하였으며 전도성 입자의 갯수가 500, 1000, 2000, 4000개/$\textrm{mm}^2$이며 크기가 5, 7, 12$\mu\textrm{m}$이었다. ACA 처리의 결과 입자 크기가 5$\mu\textrm{m}$이고 입자 밀도는 4000개/$\textrm{mm}^2$일 경우가 대단히 낮은 접촉 저항 및 가장 안정된 본딩 특성을 나타냈었다.

• 한국염색가공학회지
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• 제21권1호
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• pp.1-9
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• 2009

A lot of research has been made over the recent decade to develop testing packages with antimicrobial properties to improve food safety. In this study, a new method, experimental device and technology for environmental corresponding packages of polypropylene (PP) film has been developed to provide effective temperature buffering during the transport/long-term storage of grains or foodstuffs from the supplier to the market. This quantitatively optimized mixing system enabled to produce PP films with the 700$\sim$1,400d (width;1.5$\sim$3mm, thickness;0.01$\sim$0.5mm). In the whole mixing systems, the finely-granulated inorganic illite and PP virgin chip for master batch (M/B) chip was calculated by digital measurement methods, and then the M/B chip for PP film was adapted through a air jet and PP grinding method. The prepared PP film was characterized with tensile strength and elongation, far infrared radiation (FIR) emissivity, antimicrobial activity and deodorization properties. The results revealed that the two differently grain-sized illite could be show homogeneously dispersed on PP chip surface, and as the increasing of illite content, the FIR emissivity and the anion emission rate of film was increasingly improved. In both of 325 and 1,500 mesh-sized illite contained PP chip, of course the antimicrobial activity was good. But the ultimate deodorization rate for ammonia gas of PP film were found to be approximately the same.

• Korean Chemical Engineering Research
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• 제44권5호
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• pp.513-519
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• 2006

본 연구에서는 유리(glass)와 석영(quartz)을 재질로 사용하여 MEMS(micro-electro mechanical systems) 공정을 통해 전기영동(electrophoresis)을 위한 microchip을 제작하였다. UV 광이 실리콘(silicon)을 투과하지 못하는 점에 착안하여, 다결정 실리콘(polycrystalline Si, poly-Si) 층을 채널 이외의 부분에 증착시킨 광 차단판(optical slit)에 의해 채널에만 집중된 UV 광의 신호/잡음비(signal-to-noise ratio: S/N ratio)를 크게 향상시켰다. Glass chip에서는 증착된 poly-Si 층이 식각 마스크(etch mask)의 역할을 하는 동시에 접합표면을 적절히 형성하여 양극 접합(anodic bonding)을 가능케 하 였다. Quartz 웨이퍼에 비해 불순물을 많이 포함하는 glass 웨이퍼에서는 표면이 거친 채널 내부를 형성하게 되어 시료용액의 미세한 흐름에 영향을 미치게 된다. 이에 따라, HF와 $NH_4F$ 용액에 의한 혼합 식각액(etchant)을 도입하여 표면 거칠기를 감소시켰다. 두 종류의 재질로 제작된 채널의 형태와 크기를 관찰하였고, microchip electrophoresis에 적용한 결과, quartz과 glass chip의 전기삼투 흐름속도(electroosmotic flow velocity)가 0.5와 0.36 mm/s로 측정되었다. Poly-Si 층에 의한 광 차단판의 존재에 의해, peak의 S/N ratio는 quartz chip이 약 2배 수준, glass chip이 약 3배 수준으로 향상되었고, UV 최대흡광 감도는 각각 약 1.6배 및 1.7배 정도 증가하였다.

• 대한의용생체공학회:의공학회지
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• 제28권2호
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• pp.244-249
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• 2007

Fluidic conditions for the separation of phases were surveyed in a microfluidic aqueous two-phase extraction system. The infusion ratio between polyethylene glycol (PEG) and dextran solution defines the concentrations of each polymer in micro-channel, which determine the phase-separation. The appropriate ratio between PEG (M.W. 8000, 10%, w/v) and dextran T500 (M.W. 500000, 5%, w/v) in order to perform the separation of phases of both polymers was observed as changing the mixed ratio of both polymers. Based on the fluidic conditions, stable two-phase solutions were obtained within 4% to 8% and 3% to 1% of PEG and dextran, respectively. In addition, the characteristics of the two-phase were discussed. The separation technique studied in the paper can be applied for the implementation of a lab-on-a chip which can detect various biological entities such cells, bacterium, and virus in an integrated manner using built in a biosensor inside the chip.

• 대한전자공학회논문지
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• 제25권9호
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.463-470
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• 2014

A Verilog model is proposed for transmission lines to perform the all-Verilog simulation of high-speed chip-to-chip interface system, which reduces the simulation time by around 770 times compared to the mixed-mode simulation. The single-pulse response of transmission line in SPICE model is converted into that in Verilog model by converting the full-scale analog signal into an 11-bit digital code after uniform time sampling. The receiver waveform of transmission line is calculated by adding or subtracting the single-pulse response in Verilog model depending on the transmitting digital code values with appropriate time delay. The application of this work to a USB 2.0 high-speed PHY interface reduces the simulation time to less than three minutes with error less than 5% while the mixed-mode simulation takes more than two days for the same circuit.

• Journal of the Optical Society of Korea
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• 제17권1호
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• pp.44-49
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• 2013

A transimpedance amplifier (TIA)-optical receiver (Rx) using two intersecting active feedback system with regulated-cascode (RGC) input stage has been designed and implemented for optical interconnects. The optical TIA-Rx chip is designed in a 0.13 ${\mu}m$ CMOS technology and works up to 10 Gbps data rate. The TIA-Rx chip core occupies an area of 0.051 $mm^2$ with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/${\surd}$Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 $GHz{\Omega}/mW$.

• Current Optics and Photonics
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• 제2권6호
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• pp.576-581
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• 2018

A new approach for identification of a microwave frequency using an integrated optical waveguide chip, combined with a phase modulator (PM) and two microring resonators (MRRs), is proposed, theoretically deduced, and verified. By wavelength tuning to set the PM under the condition of a double side band (DSB), the measurement range can be started from the dc component, and the measurement range and response slope can be adjusted by designing the radius and transmission coefficient of the MRR. Simulations reveal that the amplitude comparison function (ACF) has a monotonic relationship from dc to 32.5 GHz, with a response slope of 5.15 dB under conditions of DSB modulation, when the radius values, transmission coefficients, and the loss factors are designed respectively as $R_1=400{\mu}m$, $R_2=600{\mu}m$, $t_1=t_2=0.63$, and ${\gamma}_1={\gamma}_2=0.66$. Theoretical calculations and simulation results both indicate that this new approach has the potential to be used for measuring microwave frequencies, with the advantages of compact structure and superior reconfigurability.