• 제목/요약/키워드: two representation of 3-digit number

검색결과 3건 처리시간 0.019초

분동을 활용한 문제의 수학적 탐구 (Mathematical Exploration of Counterweight Activities)

  • 김상룡
    • 한국초등수학교육학회지
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    • 제14권1호
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    • pp.123-134
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    • 2010
  • 본 논문에서는 평형저울을 이용하여 정확한 무게를 측정하기 위한 분동설계 과정에서 적용되는 수학적 내용 및 그 표현들에 대해 탐구하였다. 이 일련의 과정에서 일어날 수 있는 수학 장면과 아이디어 탐구, 2진법, 3진법의 2가지 다른 표현에 대한 이해 등을 포함한 구체적인 수학적 사고의 형성과정을 설명하고 분석한다. 이러한 과정을 현장에 적용하여 학습자의 수학적 사고의 발달과 수학적 성향을 개선시키는데 조금의 보탬이 되고자 하는데 그 목적이 있다.

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Representation of hand written decimal digits by n sequence of fuzzy sets

  • Moon, Byung-Soo;Hwang, In-Koo
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • 제2권3호
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    • pp.237-241
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    • 2002
  • In this paper, we describe how to represent hand witten decimal digits by a sequence of one to five fuzzy sets. Each fuzzy set represents an arc segment of the digit and is a Cartesian product of four fuzzy sets; the first is fur the arc length of the segment, the second is for the arc direction, the third is fur the arc shape, and the fourth is a crisp number indicating whether it has a junction point and if it has an end point of a stroke. We show that an arbitrary pair of these sequences representing two different digits is mutually disjoint. We also show that various forms of a digit written in different styles can be represented by the same sequence of fuzzy sets and hence the deviations due to different writers can be modeled by using these fuzzy sets.

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

  • Kamal, Hassan;Lee, Joo-Hyun;Koo, Bon-Tae
    • ETRI Journal
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    • 제33권5호
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    • pp.695-703
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    • 2011
  • The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.