• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.229.1-229.1
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• 2016

본 연구에서는 Hole Transporting Layer(HTL)와 Electron Transporting Layer(ETL)의 두께에 의한 특성을 비교해보기 위해서 각각 0, 10, 20 nm로 HTL, ETL 두께를 달리한 형광 OLED소자를 제작하였다. ETL의 두께가 얇아질수록 $V_{TH}$ 값은 2.5V에서 0.9 V로 낮게 나타났고 소자의 전체 두께와 on voltage는 비례한다는 특성을 발견할 수 있었다. HTL과 ETL이 두꺼울수록 각 layer에서 carrier들의 이동에 delay가 생기고 emission layer에서 표면까지 거리가 생기기 때문이다. ETL의 두께가 두꺼울수록 높은 luminance 값을 나타내는 차이를 보여주고 있다. Hole에 비해 이동도가 작은 electron은 emission layer까지 늦게 전달되어, EML내에서 비교적 cathode쪽에 가까운 곳에서 exciton이 형성되기 때문이다. CE에도 더 두꺼운 ETL을 가진 소자가 더 높은 CE값 가짐을 확인할 수 있다. 모든 소자가 $200mA/cm^2$에서 가장 높은 CE값을 나타낸 이유는 $200mA/cm^2$에서 electron-hole 결합이 만들어내는 exciton형성이 가장 많기 때문이다. PE, QE도 ETL 두께가 두꺼울수록 특성을 향상이다. 결론적으로 ETL의 두꺼울수록 current density값이 감소함을 보이고 있는 반면 turn on voltage, luminance, efficiency 증가함을 볼 수 있다.

• Journal of Electrical Engineering and Technology
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• v.12 no.2
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• pp.632-642
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• 2017

This paper presents an improved approach towards reducing the switching loss of insulated gate bipolar transistors (IGBTs) for a medium-capacity-class power conditioning system (PCS). In order to improve the switching performance, the switching operation is analyzed, and based on this analysis, an improved switching method that reduces the switching time and switching loss is proposed. Compared to a conventional gate drive scheme, the switching loss, switching time, and delay are improved in the proposed gate driving method. The performance of the proposed gate driving method is verified through several experiments.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.96.6-96
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• 2001

A high peak power demand at substations will result under Moving Block Signalling (MBS) when a dense queue of trains begins to start from a complete stop at the same time in an electrified railway system. This may cause the power supply interruption and in turn affect the train service substantially. In a recent study, measures of Starting Time Delay (STD) and Acceleration Rate Limit (ARL) are the possible approaches to reduce the peak power demand on the supply system under MBS. Nevertheless, there is no well-defined relationship between the two measures and peak power demand reduction (PDR). In order to attain a lower peak demand at substations on different traffic conditions and system requirements, an expert system is one of the possible approaches to procure the appropriate use of peak demand reduction measures ...

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1161-1164
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Proceedings of the IEEK Conference
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• summer
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• pp.70-73
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• 2004

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array (FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of information and communication convergence engineering
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• v.10 no.3
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• pp.269-275
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• 2012

In this paper, we proposed a novel location estimation algorithm based on the concept of space-time signature matching in a moving target environment. In contrast to previous fingerprint-based approaches that rely on received signal strength (RSS) information only, the proposed algorithm uses angle, delay, and RSS information from the received signal to form a signature, which in turn is utilized for location estimation. We evaluated the performance of the proposed algorithm in terms of the average probability of error and the average error distance as a function of target movement. Simulation results confirmed the effectiveness of the proposed algorithm for location estimation even in moving target environment.

• Journal of Korean Port Research
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• v.8 no.2
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• pp.1-35
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• 1994

The main arterial which runs through the in City of Pusan, carries about 60% of downtown traffic or more, maintains about 20% yearly increase in traffic is severely suffering from the traffic congestion because of concentrated traffic volumes regardless of peak-time periods. The purpose of this study was to grasp the traffic, geometric, and signal conditions of the main arterial through the Videologging System Techniques, perform the transportation system analyses, and finally suggest the improvements which could increase the travel capacity, reduce the average delay and fuel consumption with the optimal conditions of signal system. The following conclusions were drawn : firstly the traffic system should be shifted for the travel distribution on the arterial during the peak time periods, secondly the roadway system of the arterial reviewed for left-turn traffic during the peak time periods, and thirdly the signal system of intersection reconstructed for signal optimization or progression within the range of cycle length suggested.

• Journal of Korean Society of Transportation
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• v.20 no.5
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• pp.23-31
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• 2002

The headway of vehicles entering an intersection is closely related with the saturation flow rate and is a basic parameter required for determining the saturation headway and the start-up lost delay. Since such headway value reflects the drivers' behaviors and features of the intersection, all intersections don't have an equal value, but are affected by number and location of their lanes, changing types, local characteristics and time zone. Accordingly, this study attempted to suggest proper values on the basis of data by investigating headway in lanes. Number of exclusive through lanes was divided into single lane, double lanes and triple lanes, the locations of lanes were divided into inside lane, central lane and outside lane. As a result of investigating the headway, single through lane, double through lanes-inside lane, and triple through lane-outside lane showed as 1.73 sec., 1.71 sec. and 1.93sec., respectively. The result of calculating the area factor of business areas by fixing 1.00 for the residental area and applying relation between headway and saturation flow rate was 0.96. In the case of start-up lost delay lead dual left turn and directional separation were 1.41 sec. and 3.27 sec., respectively, showing the great difference. Therefore, different start-up lost delay according to changing type should be applied.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.288-298
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• 2003

We consider a window-controlled selective-repeat ARQ scheme for error control between two adjacent nodes lying on a communication path. In this scheme, each packet to be transmitted is endowed with a serial number in a cyclic and sequential fashion. In turn, the transmitting node is not allowed to transmit a packet belonging to a window before every packet in the previous window is positively acknowledged. Such postponement of packet transmission incurs a degradation in throughput and delay performance. In this paper, aiming at improving packet delay performance, we employs a supplement scheme in which a serial number is duplicated within a frame. Classifying duplication rules into fixed, random and adaptive categories, we present candidate rules in each category and evaluate the packet delay performance induced by each duplication rule. From numerical examples, we observe that duplicating serial numbers, especially ADR-T2 effectively reduces mean packet delay for the forward channel characterized by a low packet error rate. We also reveal that such delay enhancement is achieved by a high probability of hitting local optimal window size.