• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.6
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• pp.321-326
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• 2016

Minimizing the carrier recombination and electrical loss through surface passivation is required for high efficiency c-Si solar cell. Usually, $SiN_X$, $SiO_X$, $SiON_X$ and $AlO_X$ layers are used as passivation layer in solar cell application. Silicon oxide layer is one of the good passivation layer in Si based solar cell application. It has good selective carrier, low interface state density, good thermal stability and tunneling effect. Recently tunneling based passivation layer is used for high efficiency Si solar cell such as HIT, TOPCon and TRIEX structure. In this paper, we focused on silicon oxide grown by various the method (thermal, wet-chemical, plasma) and passivation effect in c-Si solar cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.133-133
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• 2009

It is desirable to choose a high-k material having a large band offset with the tunneling oxide and a deep trapping level for use as the charge trapping layer to achieve high PIE (Programming/erasing) speeds and good reliability, respectively. In this paper, charge trapping and tunneling characteristics of high-k hafnium oxide ($HfO_2$) layer with various thicknesses were investigated for applications of tunnel barrier engineered nonvolatile memory. A critical thickness of $HfO_2$ layer for suppressing the charge trapping and enhancing the tunneling sensitivity of tunnel barrier were developed. Also, the charge trap centroid and charge trap density were extracted by constant current stress (CCS) method. As a result, the optimization of $HfO_2$ thickness considerably improved the performances of non-volatile memory(NVM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.751-754
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• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.199-202
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• 2004

NFGM(Nano-Floating Gate Memory) is a very prospective candidate memory for the next generation with MRAM, PRAM, PoRAM. Among these memory devices for the next generation, NFGM has a lot of merits such as a simple low cost fabrication process, improved retention time, lower operating voltages, high speed program/erase time and so on. Therefore, many intensive researches for NFGM have been performed to improve device performance and reliability, which depends on the ability to control particle size, size distribution, crystallity, areal particle density and tunneling oxide quality. In this paper, we investigate the researches for NFGM up to recently.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.79-87
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• 1998

Nitrided oxides which have been investigated as alternative gate oxide for metal-oxide-semiconductor field effect devices were grown by two-step process using N$_{2}$O gas, and were chaacterized via a fowler-nordheim tunneling(FNT) electron injection technique. Electrical characteristics of nitrided gate oxides were superior to that of control oxides.Further, the FNT electron injection into the nitrided gate oxides reveals that gate oxides degrade more both if electrons were foreced to inject from the gate metal and if thicker nitrided gate oxides were used in the thickness range of 90~130.angs.. Models are suggested to explain these phenomena.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.323-329
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• 2017

This reports the electrical behavior, bonding structure and Schottky contact of gallium-zinc-oxide (GZO) thin film annealed at $100{\sim}400^{\circ}C$. The mobility of GZO with high density of PL spectra and crystal structure was also increased because of the structural matching between GZO and Si substrate of a crystal structure. However, the GZO annealed at $200^{\circ}C$ with an amorphous structure had the highest mobility as a result of a band to band tunneling effect. The mobility of GZO treated at low annealing temperatures under $200^{\circ}C$ increased at the GZO with an amorphous structure, but that at high temperatures over $200^{\circ}C$ also increased when it was the GZO of a crystal structure. The mobility of GZO with a Schottky barrier (SB) was mostly increased because of the effect of surface currents as well as the additional internal potential difference.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.