• Title/Summary/Keyword: traps saturation

Search Result 5, Processing Time 0.018 seconds

Static I-V Characteristics of Optically Controlled GaAs MESFET's with Emphasis on Substrate-induced Effects

  • Murty, Neti V.L. Narasimha;Jit, S.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.6 no.3
    • /
    • pp.210-224
    • /
    • 2006
  • A new analytical model for the static I-V characteristics of GaAs MESFET’s under optically controlled conditions in both linear and saturation region is presented in this paper. The novelty of the model lies in characterizing both photovoltaic (external, internal) and photoconductive effects. Deep level traps in the semi insulating GaAs substrate are also included in this model. Finally, effect of backgate voltage on I-V characteristics is explained analytically for the first time in literature. Small signal parameters of GaAs MESFET are derived under both dark and illuminated conditions. Some of the results are compared with reported experimental results to show the validity of the proposed model. Since accurate dc modeling is the key to accurate ac modeling, this model is very useful in the designing of photonic MMIC’s and OEIC’s using GaAs MESFET.

Dark Conductivity in Semi-Insulating Crystals of CdTe:Sn

  • Makhniy, V.P.;Sklyarchuk, V.M.;Vorobiev, Yu.V.;Horley, P.P.
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.15 no.2
    • /
    • pp.243-248
    • /
    • 2015
  • We prepared semi-insulating CdTe for radiation detectors by isothermal annealing of single crystals grown by Bridgeman technique in a sealed quartz container filled with Sn vapor. The resistivity of CdTe:Sn samples thus obtained was of order of $10^{10}Ohm{\cdot}cm$ at room temperature with electrons lifetime of $2{\times}10^{-8}$ s, which is appropriate for the applications desired. Analysis of electric transport characteristics depending on temperature, sample thickness and voltage applied revealed the presence of traps with concentration of about $(4-5){\times}10^{12}cm^{-3}$ with the corresponding energy level at 0.8 - 0.9 eV counted from the bottom of conduction band. The conductivity was determined by electron injection from electrodes in space charge limited current mode.

Hot-Carrier Degradation of NMOSFET (NMOSFET의 Hot-Carrier 열화현상)

  • Baek, Jong-Mu;Kim, Young-Choon;Cho, Moon-Taek
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.10 no.12
    • /
    • pp.3626-3631
    • /
    • 2009
  • This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

The Shift of Threshold Voltage and Subthreshold Current Curve in LDD MOSFET Degraded Under Different DC Stress-Biases (DC 스트레스에 의해 노쇠화된 LDD MOSFET에서 문턱 전압과 Subthreshold 전류곡선의 변화)

  • Lee, Myung-Buk;Lee, Jung-Il;Kang, Kwang-Nham
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.26 no.5
    • /
    • pp.46-51
    • /
    • 1989
  • The degradation phenomena induced by hot-carrier injection was studied from the shift of threshold voltage and subthreshold current curve in LDD NMOSFET degraded under different DC stress-biases. Threshold voltage shift ${Delta}V_{tex}$ defined in saturation region was separated into contri butions due to trapped oxide charge $V_{ot}$ and interface traps ${Delta}V_{it}$ generated from midgap to threshold voltage. Under th positive stress electric field (TEX>$V_g>V_d$) condition, the shift of threshold voltage was attributed to the electrons traped ar gate oxide but subthreshold swing was not negative stress electric field ($V_g) condition, holes seems to be injected positive charges so threshold voltage and subthreshold swing were increased.

  • PDF

Analysis of the Current-voltage Curves of a Cu(In,Ga)Se2 Thin-film Solar Cell Measured at Different Irradiation Conditions

  • Lee, Kyu-Seok;Chung, Yong-Duck;Park, Nae-Man;Cho, Dae-Hyung;Kim, Kyung-Hyun;Kim, Je-Ha;Kim, Seong-Jun;Kim, Yeong-Ho;Noh, Sam-Kyu
    • Journal of the Optical Society of Korea
    • /
    • v.14 no.4
    • /
    • pp.321-325
    • /
    • 2010
  • We analyze the current density - voltage (J - V) curve of a Cu(In,Ga)$Se_2$ (CIGS) thin-film solar cell measured at different irradiation power densities. For the solar-cell sample investigated in this study, the fill factor and power conversion efficiency decreased as the irradiation power density (IPD) increased in the range of 2 to 5 sun. Characteristic parameters of solar cell including the series resistance ($r_s$), the shunt resistance ($r_{sh}$), the photocurrent density ($J_L$), the saturation current density ($J_s$) of an ideal diode, and the coefficient ($C_s$) of the diode current due to electron-hole recombination via ionized traps at the p-n interface are determined from a theoretical fit to the experimental data of the J - V curve using a two-diode model. As IPD increased, both $r_s$ and $r_{sh}$ decreased, but $C_s$ increased.