• Journal of Power Electronics
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• v.15 no.2
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• pp.389-398
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• 2015

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.191-192
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• 2014

Multiple output converters (MOCs) are widely used for applications which require various levels of the output voltages due to their benefits in cost, volume, and efficiency. However, most of the MOCs developed so far can regulate only one output tightly and require as many secondary windings in the transformer as the number of the outputs. In this paper, a novel Time Division Multiple Control (TDMC) method to regulate all the outputs in high precision is proposed and applied for the multiple output battery charger based on the phase shift full bridge topology to charge a multiple number of batteries at one time. The proposed converter can charge three different kinds of batteries or same kind of batteries in different state of charges (SOCs) by using constant current/constant voltage (CC/CV) charge mode independently. At the same time it can provide an even degree of tight regulation for each output to satisfy the strict ripple requirement of the battery. The validity and feasibility of the proposed method are verified through the experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.372-375
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• 2021

A three-leg inverter-type isolated DC-DC Converter that can use 220 and 440 V grid input voltages is introduced. The secondary circuit structure of the proposed topology is center-tap, which is the same as the conventional phase-shifted full-bridge converter. However, the primary circuit structure is composed of a three-leg inverter structure and a transformer, in which two primary windings are connected in series. The proposed circuit structure has a wider input voltage range than the conventional phase-shifted full-bridge converter, and the circulating-current on the primary-side is reduced. In addition, the voltage stress at the secondary rectifier is greatly improved, and high efficiency can be achieved at a high input voltage by removing the snubber circuit added to the conventional converter. Prototype converters with input DC of 311 V, output of 622 V, and 50 V and 6 kW class specifications were designed and manufactured to verify the validity of the proposed topology; the experimental results are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.