• Journal of Power Electronics
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• v.11 no.5
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• pp.677-687
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• 2011

In this paper a cycloconverter-type high frequency transformer link inverter with a reduced switch count is analyzed and designed. The proposed topology consists of an H-bridge inverter at the transformer's primary side and a cycloconverter with three bidirectional switches at the secondary. All of the switches of the cycloconverter operate in non-resonant zero voltage and zero current switching modes. To overcome a high voltage surge problem resulting from the transformer leakage inductance, phase angle control based on natural commutation is employed. The effectiveness of the proposed inverter is verified by constructing s 750W prototype. Experimentally, the inverter is able to supply a near sinusoidal output voltage with a total harmonic distortion of less than 1%. For comparison, a PSpice simulation of the inverter is also carried out. It was found that the experimental results are in very close agreement with the simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.5
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• pp.422-428
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• 2013

Recently, we use a static synchronous compensator(STATCOM) with cascaded H-bride topologies, because it is easy to increase capacity and to reduce total harmonic distortion(THD). When we use equipment for reactive power compensation, dc-link voltage unbalances occur from several reasons although loads are balanced. In the past, switching pattern change of single phase inverter and reference voltage magnitude change of inverter equipped with power sensor have been used for dc-link voltage balance. But previous methods are more complicated and expensive because of additional component costs. Therefore, this paper explains reasons of dc-link voltage unbalance and proposes solution. This solution is complex method that is composed of reference voltage magnitude change of inverter without additional hardware and shifted phase angle of inverter reference voltages change. It proves possibility through 1000[KVA] system simulation.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.163-166
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• 2001

In this paper, a two-level switching algorithm ov the deadbeat to control PWM inverter is proposed. A modified algorithm of the deadbeat is suitable for the UPS system. Two levels in the pulse pattern are used. This scheme allows the use of higher switching frequency for a given computation time delay, which results in lower total harmonic distortion at the output. The proposed control scheme is implemented using TMS320F240 DSP for controlling on inverter.

• Journal of Power Electronics
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• v.6 no.2
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• pp.146-162
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• 2006

This paper deals with the analysis, design and implementation of an AC-DC Zeta converter in discontinuous current mode (DCM) of operation used for power quality improvement at AC mains in direct torque controlled (DTC) permanent magnet synchronous motor (PMSM) drives. The designed Zeta converter feeds a direct torque controlled PMSM drive system. Modeling and simulation is carried out in a standard PSIM software environment. Test results are obtained on the developed prototype Zeta converter using DSP ADMC401. The results obtained demonstrate the effectiveness of the Zeta converter in improving power quality at AC mains in the PMSM drive system.

• Journal of Power Electronics
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• v.15 no.4
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• pp.951-963
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• 2015

In this paper, a new symmetric multilevel inverter is proposed. A simple structure for the cascaded multilevel inverter topology is also proposed, which produces a high number of levels with the application of few power electronic devices. The symmetric multilevel inverter can generate 2n+1 levels with a reduced number of power switches. The basic unit is composed of a single and double source unit (SDS-unit). The application of this SDS-unit is for reducing the number of power electronic components like insulated gate bipolar transistors, freewheeling diodes, gate driver circuits, dc voltage sources, and blocked voltages by switches. Various new algorithms are recommended to determine the magnitude of dc sources in a cascaded structure. Furthermore, the proposed topology is optimized for different goals. The proposed cascaded structure is compared with other similar topologies. For verifying the performance of the proposed basic symmetric and cascaded structure, results from a computer-based MATLAB/Simulink simulation and from experimental hardware are also discussed.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.1
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• pp.30-37
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• 2011

This paper presents a circuit configuration of multilevel inverter to synthesize a large number of output voltage levels by connecting a full-bridge inverter to a 5-level inverter in series. We analyze the characteristics by computer-aided simulations and experiments when it has input voltage sources which have the same and the power of three in the amplitude. In addition, it is compared with the conventional transformer based multilevel inverter.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.199-200
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• 2014

본 논문에서는 저 용량에서 많이 사용되는 임계 도통 모드 부스트 역률 보상 회로의 새로운 제어 방법을 제안한다. 제안하는 제어 방법은 임계 도통 모드로 동작 시에 회로의 주요 파형들을 수식적으로 분석하여 입력 전류가 입력 전압을 추종할 수 있는 최적의 온-시간을 도출하는 방식이다. 100W 급 하드웨어를 통하여 제안하는 제어 방법의 실험 결과를 검증하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.367-368
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• 2015

This paper introduces a shunt active power filter with a small DC bus capacitor by adding additional low-pass filter (LPF). The DC link voltage fluctuation is impressively suppressed with a small value in spite of the low value of DC-link capacitor under the steady-state condition. Consequently, the cost and volume of power converter are significantly reduced thanks to the reduced value of DC-bus capacitor. On the other hand, an indirect control strategy is used to maintain grid-side current when non-linear loads are connected to the system. By using proportional-integral (PI) and modified repetitive controller (RC) in dq0 frame, the calculation time is greatly decreased by 6 times compared with the conventional RC, and the number of measurement devices is also minimized. As a result, the acquired total harmonic distortion (THD) is lower than 2% regardless of the load conditions. Simulation results are carried out in order to verify the effectiveness of the proposed control strategy.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.524-525
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• 2015

본 논문은 계통연계형 소용량 태양광 인버터에 적용된 AFD(Active Frequency Drift) 기반의 단독 운전 검출 기법을 제안한다. 태양광 시스템에 일반적인 인버터 토폴로지를 사용한 경우, 무효전력 주입을 이용하여 단독운전 검출이 가능하다. 하지만 무효전력의 제어가 불가능한 인버터를 사용한 경우에는 기존의 무효전력을 이용하는 단독운전 검출기법을 사용할 수 없다. 무효전력의 제어가 불가능한 인버터 토폴로지에 새로운 스위칭 기법을 적용하면 무효전력을 주입한 효과를 얻을 수 있고, 이를 통해 기존의 AFD 방식을 응용하여 단독운전 검출이 가능한 새로운 검출기법을 제안하였다. 제안하는 검출기법은 기존의 AFD 방식보다 인버터 출력전류의 THD (Total Harmonic Distortion)를 개선할 수 있는 장점이 있다. 제안하는 기법의 성능을 시뮬레이션을 통해 확인하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.59-60
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• 2015

본 논문에서는 3-Level NPC(Neutral Point Clamped) 인버터에서 ZDPWM(Zero Dead Time Pulse Width Modulation) 기법에 대해서 제안한다. 3-Level NPC 인버터에서 기존 PWM 기법은 각 스위치는 서로 상보적인 동작을 수행하고, 반도체 스위칭 소자 특성상 Rise Time과 Fall Time의 시간차이로 인하여 단락사고를 방지하기 위해 스위칭 신호의 Rising Edge에 데드타임을 인가하여 단락을 방지한다. 그러나 이러한 데드타임은 지령 스위칭 신호와 실제 스위칭 신호의 오차로 인하여 출력 전압 및 전류에 왜곡이 발생하고, 이러한 왜곡으로 인하여 시스템의 오작동 및 직류링크단 전압의 불평형의 원인이 된다. 제안하는 PWM기법은 지령전압과 출력전류의 위상에 따라 영역을 나눈 후 전류의 방향에 따라 옵셋 전압을 생성하여 새로운 지령전압을 만들어 각 스위치에 스위칭 신호를 인가한다. 제안한 기법에 타당성을 증명하기 위해 시뮬레이션을 통해 검증하였다.