• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.813-815
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• 2008

We prepared highly transparent and conductive Oxide/Metal/Oxide(OMO) multilayer by sputtering and developed wet etching process of OMO with a clear edge shape for the first time. The transmittance and sheet-resistance of the OMO are about 89% and $3.3\;{\Omega}/sq.$, respectively. We adopted OMO as a gate electrode of transparent TFT (TTFT) array and integrated OLED on top of the TTFT to result in high aperture ratio of bottom emission AM-OLED.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.198-201
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• 2006

The optimization of poly-Si TFT process on metal foil for UTL AMOLED was systematically investigated. The improvement in device performance of poly-Si TFT on metal foil was achieved by optimizing the dopant activation condition and gate dielectric structure. Hence, the world first flexible full color 5.6-inch AMOLED with top emission mode on poly-Si TFT stainless steel foil is demonstrated.

• Journal of Information Display
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• v.10 no.4
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• pp.137-142
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• 2009

Transparent top-gate Al-Zn-Sn-O (AZTO) thin-film transistors (TFTs) with an $Al_2O_3$ protective layer (PL) on an active layer were studied, and a transparent 2.5-inch QCIF+AMOLED (active-matrix organic light-emitting diode) display panel was fabricated using an AZTO TFT backplane. The AZTO active layers were deposited via RF magnetron sputtering at room temperature, and the PL was deposited via two different atomic-layer deposition (ALD) processes. The mobility and subthreshold slope were superior in the TFTs annealed in vacuum and with oxygen plasma PLs compared to the TFTs annealed in $O_2$ and with water vapor PLs, but the bias stability of the TFTs annealed in $O_2$ and with water vapor PLs was excellent.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.4
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• pp.92-102
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• 2003

To detect electrical faults of a TFT (Thin Film Transistor) panel for the LCD (Liquid Crystal Display), techniques of converting electric field to an image are used One of them is the PDLC (polymer-dispersed liquid crystal) modulator which changes light transmittance under electric field. The advantage of PDLC modulator in the electric field detection is that it can be used without physically contacting the TFT panel surface. Specific pattern signals are applied to the data and gate electrodes of the panel to charge the pixel electrodes and the image sensor detects the change of transmittance of PDLC positioned in proximity distance above the pixel electrodes. The image represents the status of electric field reflected on the PDLC so that the characteristic of the PDLC itself plays an important role to accurately quantify the defects of TFT panel. In this paper, the image of the PDLC modulator caused by the change of electric field of the pixel electrodes on the TFT panel is acquired and how the characteristics of PDLC reflect the change of electric field to the image is analyzed. When the holding time of PDLC is short, better contrast of electric field image can be obtained by changing the instance of applying the driving voltage to the PDLC.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1001-1006
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• 2005

A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.

• ETRI Journal
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• v.31 no.6
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• pp.653-659
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• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• Journal of the Korean Society of Safety
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• v.27 no.3
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• pp.111-116
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• 2012

This study is about the quantitative safety assessment of hydrogen station in Korea operating with on-site type. This was written by background information that before qualitative safety assessment to write. For the qualitative safety assessment method, the study used FMEA(failure mode & effect analysis) and HAZOP(hazard & operability), and adopted the FTA(fault tree analysis) as the quantitative safety assessment method. To write the FTA, we wrote FT by Top event that hydrogen leakage can be called most serious accident of hydrogen station. Each base event collect reliability data by reliability data handbook, THERP-HRA and estimation of the engineering. Assessment looked at the high frequency and the possible risk through Gate, Importance, m.cutsets analysis.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1339-1340
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• 2007

본 연구에서는 이종 차원 나노선과 나노입자의 결합에 따른 단일 나노선 소자의 전기적 특성 및 메모리 효과를 연구하였다. 열증착법으로 성장 된 p 형 Si 나노선에 Atomic Layer Deposition (ALD) 방법으로 10nm의 $Al_{2}O_{3}$를 증착한 후 Low Precensure - Chemical Vapor Deposition (LP-CVD)를 이용하여 Polycrystalline Sicon(Poly-Si)을 Si 나노선 위에 5nm 증착하고 습식 에칭법을 이용하여 poly Si 내의 $SiO_x$를 제거하여 Si 나노입자를 Si 나노선 위에 형성시켰다. 그 후 포토리소그래피 공정을 이용하여 Top gate 형태의 나노선-나노입자 이종결합 Field-Effect Transistor (FET) 소자를 제작하여 게이트 전압에 따른 드레인 전류-전압($I_{DS}-V_{DS}$)의 변화를 측정하여 나노선의 전기 소자로서의 특성을 확인하고, 게이트 전압을 양방향으로 swing 하면서 인가하여 $I_{DS}$ 전류 특성이 변화하는 것을 통해 메모리 효과를 조사하였다. 또한 나노입자의 결합이 게이트 전압의 인가 시간에 따라 드레인 전류에 영향을 미치는 것을 확인하여 메모리 소자로서의 가능성을 확인하였다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.09a
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• pp.83-88
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• 2005

유기 절연층을 갖는 유기 박막트랜지스터 (organic TFT)를 제작하여 소자 성능을 조사하였다. 유기 절연층의 형성에서는 polyvinyl 계열의 PVP(poly-4-vinylphenol)와 PVT(polyvinyltoluene)를 용질로, PGMEA (propylene glycol mononethyl ether acetate)를 용매로 사용하였다. 또한, 열경화성 수지인 poly(melamine-co-formaldehyde)를 경화제로 사용하여 유기 절연층의 cross-link 를 시도하였다. MIM 구조로 유기 절연층의 특정을 측정한 결과, PVT는 PVP에 비해 절연 특성이 떨어지는 경향을 보였다. 게이트 절연막의 제작에서 PVP를 cobpolymer 방식과 cross-linked 방식으로 실험 해 본 결과, cross-link 방식에서 낮은 누설전류 특성을 나타내었다. OTFT 제작에서는 PVP를 용질로, poly(melanine-co-formaldehyde)를 경화제로 사용한 cross-linked PVP 를 게이트 절연막으로 이용하였다. PVP copolymer($20\;wt\%$)에 $10\;wt\%$ poly(melamine- co-formaldehyde)를 혼합한 cross-linked PVP 를 게이트 절연막으로 사용하여 top contact 구조의 OTFT를 제작한 결과 약 $0.23\;cm^2/Vs$의 정공 이동도와 약 $0.4{\times}10^4$의 평균 전류점멸비를 나타내었다.