• Journal of information and communication convergence engineering
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• 제13권4호
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.17.2-17.2
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• 2010

Printed electronics is an emerging technology to realize various microelectronic devices via a cost-effective method. Here we demonstrated a high performance of p-channel and n-channel top-gate/bottom contact polymer field-effect transistors (FETs), and applications to elementary organic complementary inverter and ring oscillator circuits by inkjet processing. We could obtained high field-effect mobility more than $0.4\;cm^2/Vs$ for both of p-channel and n-channel FETs, and successfully measured inkjet-printed polymer inverters. The performance of devices highly depends on the selection of dielectrics, printing condition and device architecture. Optimized CMOS ring oscillators with p-type and n-type polymer transistors showed as high as 50 kHz operation frequency. This research was financially supported by development of next generation RFID technology for item level applications (2008-F052-01) funded by the ministry of knowledge economy (MKE).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.297-300
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• 2005

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) fabricated using sputter deposited amorphous silicon (a-Si) precursor films are investigated. The a-Si films were deposited on flexible polymer substrates using argon-helium mixture gases to minimize the argon incorporation into the film. The precursor films were then laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated pMOS TFT showed field-effect mobility of $32.4cm^2/V{\cdot}s$ and on/off ratio of $10^6$.

• Transactions on Electrical and Electronic Materials
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• 제11권4호
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• pp.190-193
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• 2010

This report covers an effective fabrication method of graphene nanoribbon for top-gated field effect transistors (FETs) utilizing electron beam lithography with a bi-layer resists (XR-1541/poly methtyl methacrylate) process. To improve the variation of the gating properties of FETs, the residues of an e beam resist on the graphene channel are successfully taken off through the combination of reactive ion etching and a lift-off process for the XR-1541 bi-layer. In order to identify the presence of graphene structures, atomic force microscopy measurement and Raman spectrum analysis are performed. We believe that the lift-off process with bi-layer resists could be a good solution to increase gate dielectric properties toward the high quality of graphene FETs.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2012년도 춘계학술발표대회
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• pp.67.2-67.2
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• 2012

Graphene is expected to have a significant impact in various fields in the foreseeable future. For example, graphene is considered to be a promising candidate to replace indium tin oxide (ITO) as transparent conductive electrodes in optoelectronics applications. We report the tunability of the wavelength of localized surface plasmon resonance by varying the distance between graphene and Au nanoparticles [1]. It is estimated that every nanometer of change in the distance between graphene and the nanoparticles corresponds to a resonance wavelength shift of ~12 nm. The nanoparticle-graphene separation changes the coupling strength of the electromagnetic field of the excited plasmons in the nanoparticles and the antiparallel image dipoles in graphene. We also show a hysteresis in the conductance and capacitance can serve as a platform for graphene memory devices. We report the hysteresis in capacitance-voltage measurements on top gated bilayer graphene which provide a direct experimental evidence of the existence of charge traps as the cause for the hysteresis [2]. By applying a back gate bias to tune the Fermi level, an opposite sequence of switching with the different charge carriers, holes and electrons, is found [3]. The charging and discharging effect is proposed to explain this ambipolar bistable hysteretic switching.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.849-851
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• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께 비에 대한 문턱전압이하 스윙 및 전도중심의 변화에 대하여 분석하고자한다. 문턱전압이하 스윙은 전도중심에 따라 변화하며 전도중심은 상하단의 산화막 두께에 따라 변화한다. 비대칭 이중게이트 MOSFET는 상단과 하단의 게이트 산화막 두께를 다르게 제작할 수 있어 문턱전압이하 스윙의 저하 등 단채널효과를 감소시키기에 유용한 소자로 알려져 있다. 본 연구에서는 포아송방정식의 해석학적 해를 이용하여 문턱전압이하 스윙을 유도하였으며 상하단의 산화막두께 비가 전도중심 및 문턱전압이하 스윙에 미치는 영향을 분석하였다. 결과적으로 문턱전압이하 스윙 및 전도중심은 상하단 게이트 산화막 두께 비에 따라 큰 변화를 나타냈다. 또한 채널길이 및 채널두께, 상하단게이트 전압 그리고 도핑분포함수의 변화에 따라 문턱전압이하 스윙 및 전도중심은 상호 유기적으로 변화하고 있다는 것을 알 수 있었다.

• 전기학회논문지
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• 제59권2호
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• pp.359-362
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• 2010

In this study, inverter logic circuits on a plastic substrate are built with two top-gate FETs in series on a single ZnO nanowire. The voltage transfer characteristics of the ZnO nanowire-based inverter logic circuit exhibit a clear inverting operation. The logic swing, gain and transition width of the inverter logic circuit is about 90 %, 1.03 and 1.2 V, respectively. The result of mechanical bending cycles of the inverter logic circuit on a plastic substrate shows that the stable performance is maintained even after many hundreds of bending cycles.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.961-963
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• 2009

a-Si process-based advanced-SPC (a-SPC) TFT has been developed and verified by manufacturing an AMOLED panel having improved cost competitiveness by using the existing a-Si infrastructure. The a-SPC TFT had superior device reliability and current drivability to a-Si TFT to meet the requirements of AMOLED backplane.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.318-321
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• 2009

We have studied transparent top gate Al-Zn-Sn-O (AZTO) TFTs with an $Al_2O_3$ protective layer (PL) on an active layer. We also fabricated a transparent 2.5 inch QCIF+AMOLED display panel using the AZTO TFT back-plane. The AZTO active layers were deposited by RF magnetron sputtering at room temperature and the PL was deposited by ALD with two different processes. The mobility and subthreshold slope were superior in the cases of the vacuum annealing and the oxygen plasma PL compared to the $O_2$ annealing and the water vapor PL, however, the bias stability was excellent for the TFTs of the $O_2$ annealing and the water vapor PL.

• 전자공학회논문지B
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• 제28B권9호
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• pp.712-718
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• 1991

In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.