• Title/Summary/Keyword: timing controller

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Dynamic PIV Measurement of Swirl Flow in a PC Fan

  • ARAMAKI Shinichiro;HAYAMI Hiroshi
    • 한국가시화정보학회:학술대회논문집
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    • 2004.12a
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    • pp.41-45
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    • 2004
  • The dynamic particle image velocimetry (PIV) is consisted of a high frequency pulse laser, high speed cameras and a timing controller. The three velocity components of flow downstream of an axial flow fan for PC cooling system are measured using the dynamic PIV system. An Axial flow fan has seven blades of 72 mm in diameter. The rotating speed is 1800 rpm. The downstream flow is visualized by smoke particles of about $0.3-1\;{\mu}m$ in diameter. The three-dimensional instantaneous velocity fields are measured at three downstream planes. The swirl velocity component was diffused downstream and the change in time-mean vorticity distribution downstream was also discussed. The spatio-temporal change in axial velocity component with the blades passing is recognized by the instantaneous vector maps. And the dynamic behavior of vorticity moving with the rotating blades is discussed using the unsteady vorticity maps.

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2색법에 의한 에멀죤 연료의 화염온도 및 soot 분포 측정에 관한 실험적 연구

  • Park, Jae-Wan;Park, Gwon-Ha;Heo, Gang-Yeol
    • 한국연소학회:학술대회논문집
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    • 1998.10a
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    • pp.103-110
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    • 1998
  • This experiment is performed to investigate the effects of the emulsion on the flame temperature and soot formation in a diesel engine. The two-color method is used to measure the flame temperature for combustion of emulsified diesel in the Rapid Compression and Expansion Machine(RCEM). The concentration of soot is estimated via calculation of the KL factor. The solenoid valve, elecronic controller and needle lift sensor are used to control the exact injection timing and duration under various operating conditions. According to the results the soot concentration is reduced with the increasing W/O while the temperature reduced. The pressure data and the flame images captured by a high speed camera show that the ignition delay of emulsified diesel increase the duration of premixed combustion. The sizes of water drops are measured to be about 10${\mu}m$ by a microscope.

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Technology Trend and Requirement of Mobile Displays Using Low-Temperature Poly-Si (LTPS) Technologies

  • Kwon, Oh-Kyong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2007.08a
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    • pp.409-412
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    • 2007
  • A lot of research for system-on-panel(SOP) have been done to integrate display systems including data driver, gate driver, timing controller, DC-DC converter, and smart functions such as embedded touch screen, ambient brightness sensing and luminance control, finger printing on the glass. Recently, the cost of an one-chip driver IC with various functions has decreased rapidly, and new mobile display interface technologies have been introduced. So it is necessary to examine the feasibility of SOP for practical mobile applications. In this paper, we will re-examine LTPS technologies for mobile displays in terms of various aspects and discuss the practical limitations on SOP technology and future technology trend of mobile displays.

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The implementation of a virtual Plant simulator for the PLC Programming (PLC 프로그래밍을 위한 가상 플랜트 시뮬레이터 구현)

  • Lee, Gi-Bum;Kim, Se-Yeon;Lee, Jin-S.
    • Proceedings of the KIEE Conference
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    • 1998.11b
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    • pp.475-477
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    • 1998
  • In this paper, the implementation of a virtual Plant simulator for the PLC programming is presented. A virtual plant simulator that replaces function of transducers (e.g. pumps and valves) consists of a personal computer and a PLC(Programmable logic controller). Input/output conponents are edited on the monitor and are operated as the field transducers. The timing process for input/output components is analyzed. The data flow between a PLC system and a virtual plant simulator is carried out.

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Silicon-based 0.69-inch AMOEL Microdisplay with Integrated Driver Circuits

  • Na, Young-Sun;Kwon, Oh-Kyong
    • Journal of Information Display
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    • v.3 no.3
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    • pp.35-43
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    • 2002
  • Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

Architecture design and FPGA implementation of a system control unit for a multiprocessor chip (다중 프로세서 칩을 위한 시스템 제어 장치의 구조설계 및 FPGA 구현)

  • 박성모;정갑천
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.12
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    • pp.9-19
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    • 1997
  • This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

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Software Implementation of Interrupt Profiler on a Servo-Motor Controller for Timing Analysis (서보 전동기 제어용 임베디드 시스템의 타이밍 분석을 위한 인터럽트 측정 소프트웨어의 구현)

  • Kim, Hee-Jin;Park, Sang-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2011.04a
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    • pp.81-84
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    • 2011
  • 서보 전동기는 탑재된 소프트웨어의 명령에 따라 제어되는 전동기로 다양한 임베디드 응용 분야에서 사용되고 있다. 여러 분야에서 사용되고 있는 만큼 각 응용 분야마다 시간, 부하에 따라 서보 전동기에 요구되는 응답성은 다양하다. 응답성에 민감한 서보 전동기의 소프트웨어를 효율적으로 구현하기 위해서는 다양한 요구사항에 대한 분석이 필수적이다. 본 논문에서는 시간 응답성이 요구되는 서보 전동기의 실제 임베디드 시스템을 위한 인터럽트 측정 소프트웨어를 구현하고, 이에 대한 결과를 제시한다.

Development of Digital Solder Station Based on PID Controller (PID 제어기를 이용한 전기인두기의 온도 제어 시스템 개발)

  • Oh, Kab-Suk
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.3
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    • pp.866-872
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    • 2010
  • In this paper, we developed a digital soldering station based on PID controller, which supply stable power by controlling the current of heater of soldering iron. The proposed system designed PID controller to converge quickly to the set up temperature by user, and regain the lost of heat by external factors quickly. PID controller, designed by Ziegler-Nichols' tuning method, decides triac's trigger timing using setting temperature and present temperature to control the phase of AC 24V power that supply to the heater. Also, we give the function that shows present temperature and setting temperature of iron, and working time by graphic LCD. And during the rest time, we decided the power saving and extension of iron tip by dropping to the optimal temperature. Two experiments had implemented in $25^{\circ}C$ laboratory to confirm the performance of proposed method. The first experiment took 12sec, 13sec, 16sec, 18sec, reaching to $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$, $480^{\circ}C$ respectively which result showed shorten of rising time than previous method. In the loading experiment of $300^{\circ}C$, $400^{\circ}C$, $480^{\circ}C$ steady state showed temperature drop of $3.8^{\circ}C$, $4.1^{\circ}C$, $4.5^{\circ}C$ which result showed the low temperature deviation than previous method.

Development of Fuzzy Travel Time Estimator for Interrupted Traffic Flow (단속류 퍼지 통행시간 추정기의 개발)

  • 오기도;김영찬
    • Journal of Korean Society of Transportation
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    • v.18 no.5
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    • pp.57-67
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    • 2000
  • Two fuzzy travel time estimators for interrupted traffic flow were developed based on field survey data and simulation data 7hat is collected from DETSIM, which is microscopic traffic simulation model that car-following theory is applied. One is FETTOS(Fuzzy Estimator of Travel Time using Occupancy and Spot speed) and the other is FETTOS(Fuzzy Estimator of Travel Speed using Volume and Occupancy). Fuzzy logic controller was applied to the estimators to deal with non-linear relationship between traffic variables and travel time. According to results of simulation and field survey. estimation of travel time can be modeled by using percent occupancy better than any other traffic variables. Detector location from storyline and signal timing Plan of intersection are affected to estimate travel time. With a few findings, the estimator was constructed and its performance was tested for observed travel time data and simulated data. FETTOS which needs signal timing plan and detector location estimates travel time with accurate better than FETSVO does. However. FETSVO has excellent transferability because the estimator needs set of input data only; volume and time mean speed.

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Design of Digital Signal Processor for Ethernet Receiver Using TP Cable (TP 케이블을 이용하는 이더넷 수신기를 위한 디지털 신호 처리부 설계)

  • Hong, Ju-Hyung;SunWoo, Myung-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.8A
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    • pp.785-793
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    • 2007
  • This paper presents the digital signal processing submodule of a 100Base-TX Ethernet receiver to support 100Mbps at TP cable channel. The proposed submodule consists of programmable gain controller, timing recovery, adaptive equalizer and baseline wander compensator. The measured Bit Error Rate is less than $10^{-12}BER$ when continuously receiving data up to 150m. The proposed signal processing submodule is implemented in digital circuits except for PLL and amplifier. The performance improvement of the proposed equalizer and BLW compensator is measured about 1dB compared with the existing architecture that removes BLW using errors of an adaptive equalizer. The architecture has been modeled using Verilog-HDL and synthesized using samsung $0.18{\mu}m$ cell library. The implemented digital signal processing submodule operates at 142.7 MHz and the total number of gates are about 128,528.