• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.05a
• /
• pp.88-90
• /
• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.6 s.348
• /
• pp.30-38
• /
• 2006

In this paper, an algerian that provisions absolute and proportional differentiation of packet delays is proposed with an objective for enhancing quality of service (QoS) in future packet networks. It features a scheme that compensates the deviation for prediction on the traffic to be arrived continuously It predicts the traffic to be arrived at the beginning of a time slot and measures the actual arrived traffic at the end of the time slot and derives the difference between them. The deviation is utilized to the delay control operation for the next time slot to offset it. As it compensates the prediction error continuously, it shows superior adaptability to the bursty traffic as well as the exponential traffic. It is demonstrated through simulation that the algorithm meets the quantitative delay bounds and shows superiority to the traffic fluctuation in comparison with the conventional non-adaptive mechanism.

• Journal of Korean Society of Transportation
• /
• v.11 no.1
• /
• pp.87-103
• /
• 1993

The subject this paper is the signal control strategy under oversaturated conditions. The nature of traffic control for oversaturation is essentially different from the standard control modes. While under non-saturated situation traffic control is needed for the sake of safety and efficiency, the throughput is essential under oversaturated conditions. Therefore berth objective and strategies differ. For an oversaturated stream the cycle time and the signal offset are thought to be of rather secondary importance. For this case the green split may well be the most important control variable to serve the excessive demand. Up to now, however, most efforts have concentrated on the strategy with the concept which lies just on the extension of Webster's. "Green-split Coordination Strategy for Over-Saturated Networks", presents newly contrived three types of strategies named Forward-coordination, Backward-coordination and Network-coordination respectively and describes the algorithms with the evaluations. The forward coordination strategy treats the forward wave of flow between two signals. The aim is to prevent the outbreak of queue due to the accumulation of temporary excess of demand in near-saturation or saturation flow. The backward coordination strategy treats the backward rave of flow between two signals. The goal is to prevent the waste of green time caused by the exit block at the upstream signal. for this purpose a feedback regulation is provided of the upstream green-split so that the inflow-outflow balance is kept zero. The resultant surplus of green time is alloted to other signal stages. Also here the examination is made of the appropriate value of the feedback control parameter. The network coordination strategy is operated to maximize the network throughput in a specific direction applying a bang-bang control at the bottleneck intersection. This is a type of intervenient control for policy reasons. For this strategy the green-split coordinations, particuarly the backward coordination, are essential as the tactical elements. In order to evaluate the preposed strategies those are compared with the latest existing strategy called saturation-degree-ratio control by the simulation experiments in an assumed 4$\times$4 grid network. The results are satisfactory showing a 10-15% reduction in delays and a 15% increase in network capacity.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.38 no.10
• /
• pp.979-984
• /
• 2010

The users who use a combined GPS/Galileo receiver will benefit from an improved availability of the combined system and a reduced dependence on one particular positioning system. However, these users must solve the problem of an offset between the time scales of GPS and Galileo (GGTO). GGTO must be analyzed for not only a navigation system but also a timing system requesting precise time service. This paper analyzes the interoperability problem in a combined GPS/Galileo timing receiver and estimates the timing performance under various assumptions. The GPS real measurements were collected by using the commercial timing receiver from Ashtech Ltd. and the Galileo measurements were generated by a simulation software. A suitable test scenario set-up and the performance in a point of timing stability was evaluated.

• Journal of the Korean Society of Fisheries and Ocean Technology
• /
• v.33 no.1
• /
• pp.46-58
• /
• 1997

The energy saving is one of the most important factors for profit in marine transportation. In order to reduce the fuel oil consumtion the ship's propulsion efficiency must be increased as possible. The propulsion efficiency depends upon a combination of an engine and a propeller. The propeller has better efficiency as lower rotational speed. This situation led the engine manufacturers to design the engine that has low speed, long stroke and a small number of cylinders. Consequently, the variation of rotational torque became larger than before because of the longer delay-time in fuel oil injection process and an increased output per cylinder. As this new trends the conventional mechanical-hydrualic governors for engine speed control have been replaced by digital speed controllers which adopted the PID control or the optimal control algorithm. But these control algorithms have not enough robustness to suppress the variation of the delay-time and the parameter perturbation. In this paper we consider the delay-time and the perturbation of engine parameters as the modeling uncetainties. Next we design the robust servo controller which has zero offset in steady state engine speed, based on H sub($\infty$) control theory. The validity of the controller was investigated through the response simulation. We used a personal computer and an analog computer as the digital controller and the engine (plant) part respectively. And, we could certify that the designed controller maintains its robust servo performance even though the engine parameters may vary.

• Journal of the Korean Graphic Arts Communication Society
• /
• v.31 no.1
• /
• pp.51-64
• /
• 2013

When it comes to current growth trend for the printing process in Asia printing market, offset printing, gravure printing and screen printing are reduced respectively -4%, -19%, -55%. In judging from the fact, the change in the printing production system from mass production on small amount to small production on mass amount is the biggest issue. For this reason, digital printing shows the significant growth. According to the increase of the growth 78% for electro photography way and 67% for ink-jet, it's not enough to catch up with digital printing which is increasing as time goes by to equip with hardware like as digital press. There's been necessary to install the BOD(Book on Demand) system which is the advanced and regular publication edit solution based on web-to-print model in the prepress, and it has made the BOD system be considered in relation to maximization of efficiency and production. Therefore, this research tries to step forward from the POD concept, which is refired to "Print along with the ordered quantities, the ordered appropriate time and the demanded place", so that it could expand the range of the printing/publishing environment using the BOD system, the order-made publication based on automatically operating template. And it tried to make the relation to digital web press on ink-jet method which is adequate to "mass production on small amount" with such advanced concept. This research also aims to use actively BOD solution model to promote the productivity of labor, and then to produce the printings across all related industries, which means to manufacture maximally the products on the shortest time at minimum place through PC equipments.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.11
• /
• pp.6863-6869
• /
• 2014

A SMT machine is used to place electronic components on a PCB precisely. To place it precisely, after a component inspection, it finds an offset value using a vision camera, and places the precise position on the PCB. In general, to inspect the components with a vision camera, the components stop in front of the camera for inspection, then move to the placement position. On the other hand, if they do not stop in front of a camera, the inspection time will be shortened and the productivity would be increased. In this thesis, when inspecting without stopping in front of a camera, the fastest way among various routes is described. For the gantry passing over a vision camera, both the distance and speed of a gantry moving trajectory were studied, and there was approximately 5% speed increment when using the method suggested in this thesis.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.3A
• /
• pp.237-246
• /
• 2007

Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.8
• /
• pp.1759-1764
• /
• 2012

This paper describes FPGA design and realization using the shading correction algorithm for a CCD scan image enhancement. The shading algorithm is used by LUT (Look-up Table). The image enhancement results from that the histogram minimum value and maximum with respect to all pixels of the CCD image should be extracted, and the shading LUT is constructed to keep constant histogram with offset data. The output of sensor be converted to corrected LUT image in preprocessing, and the converting system is realized by FPGA to be enabled to operate in real time. The result of the experimentation for the proposed system is showed to take the scanning time 2.4ms below. The system is presented to be based on a low speed processor system to scan enhanced images in real time and be guaranteed to be low cost.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.272-281
• /
• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.