• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.5
• /
• pp.431-439
• /
• 2017

An asymmetric half-bridge is one of the most promising topology in low-power application because of its small number of components and inherent zero-voltage switching capability. However, when it is designed taking into a hold-up time, it has large transformer offset current and small transformer turns-ratio, which severely decreases the total efficiency of s converter. In this paper, a new boost-integrated asymmetric half-bridge converter is proposed to solve these problems. The integrated boost converter compensates the hold-up time, thus facilitating optimal design in nominal state. As a result, the proposed converter can achieve high efficiency in nominal state. To verify the effectiveness of the proposed converter, an experiment is conducted using a 250-400 V input and 45 V/3.3 A output prototype.

• Journal of Korea Multimedia Society
• /
• v.18 no.4
• /
• pp.452-459
• /
• 2015

Three synchronization issues, i.e., phase, frequency, and symbol time, have to be properly controlled to achieve distributed beamforming gain. In this paper, the impacts of synchronization errors in distributed beamforming are analyzed for both single-carrier and OFDM systems. When the channel is constant over a symbol duration, the performance degradation due to phase offset is the same for both single-carrier and OFDM systems. For symbol timing offset in OFDM systems, high frequency subcarriers are more susceptible as compared to low frequency ones. Frequency offset is critical in OFDM systems since it leads to interference from the other subcarriers as well as power loss in the desired signal.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.1
• /
• pp.138-145
• /
• 2015

In this paper, a novel static overmodulation scheme (OVM) for space-vector PWM (SVPWM) is proposed. The proposed static OVM scheme uses the concept of adding offset voltages in linear region as well as overmodulation region to fully utilize DC-link voltage. By employing zero sequence voltage injection, the proposed scheme reduces procedures for achieving SVPWM such as complicated gating time calculation. In addition, this paper proposes a stepwise discontinuous angle movement in high modulation region in order to reduce Total Harmonic Distortion (THD). The validity of the proposed scheme is verified through theoretical analysis and experimental results.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.385-390
• /
• 2013

This paper proposes an efficient hardware architecture of CABAC for HEVC decoder. The proposed method is structured to handle two bins in one cycle, while preserving data dependencies of the CABAC. In addition, the processing time of the proposed architecture is reduced because the operation using Offset and Range is processed while the architecture reads rLPS from rLPSROM. As a result of analyzing operating frequency of the proposed CABAC architecture, the proposed architecture has improved by 40% than the previous one.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.16 no.2
• /
• pp.120-127
• /
• 2008

The constant velocity joint(CVJ) used for transmitting torque to the front wheels is an important part in automotive drive system. There are several types of constant velocity joints. Typically, they are classified by fixed and plunging constant velocity joints. The axial force generated in plunging constant velocity joints influences significantly the noise, vibration and harshness. For heaps of time, many constant velocity joint markers have been studying and developing a valid method to reduce the axial force and extensive tests have been carried out on rigs. This paper presents the analysis method to predict the axial force of a double offset constant velocity joint(DOJ), a kind of plunging constant velocity joint, and the influence of ball-cage dimension tolerance on the axial force.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.12
• /
• pp.40-48
• /
• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.5
• /
• pp.798-805
• /
• 2006

I evaluate the BER performance of downlink OFDMA systems in time variant Rayleigh Doppler fading channel, considering the carrier frequency offset and the nonlinear high power amplifier. I obtain the required output back-off of the nonlinear amplifier and value of frequency offset for good BER performance. And I also analyze the BER degradation upon Doppler fading channel.

• The Journal of Korea Robotics Society
• /
• v.8 no.2
• /
• pp.75-81
• /
• 2013

This research would investigate deeply the operation of an omni-directional mobile robot that is able to move with high acceleration. For the high acceleration performance, the vehicle utilizes the structure of Active Split Offset Casters (ASOCs). This paper is mainly focused on inverse kinematics of the structure, hardware design to secure durability and preserve the wheels' contact to the ground during high acceleration, and localization for the real time position control.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.483-484
• /
• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1998.10a
• /
• pp.187-190
• /
• 1998

The values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. The proposed controller, whenever necessary, measures the open-loop and close-loop characteristics, and then calculates the offset and sensor gain correction values based on the prepared standard measurements It is applied to the control of a flexible link system with the gain and offset calibration problems in the light sensor module for position to show the applicability. In this paper, we propose a digital controller which has the capability of calibration gain and offset adjustment using fuzzy methods.