• Journal of Preventive Medicine and Public Health
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• v.36 no.2
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• pp.101-107
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• 2003

Objectives : Dementia has emerged as a leading public health problem in elderly persons, and its early detection is important for the treatment of curable cases, and in the educational support for other family members. Although dementia screening tests are available, they have not gained widespread use in community or primary care settings. Our goal was to validate the Tine and Change (T&C) Test, -including its validity and reliability in patients, and to assess it as a simple, standardized method for the screening of dementia in the rural elderly. Methods : The participants in this study comprised of 59 patients from an urban hospital and 405 persons from a rural community aged 65 years or older. The time test evaluated the understanding of clock hands indicating 11:10, and the change test the ability to make 1,000 Won from a group of coins, consisting of one 500, seven 100, and seven 50 Won coins. The T&C ratings were validated against a reference standard based on the physician's diagnosis of the patients. The convergent validity in relation to other cognitive measure, test-retest agreement, and inter-observer reliability were assessed. To assess the relationship between the Korean Mini-Mental State Exam (K-MMSE) and the T&C Test, the mean K-MMSE scores were compared with the results of the T&C Test in the elderly from a rural community. Results The T&C Test had a sensitivity and specificity of 73.0, and 90.9%, and positive and negative predictive values of 93.1, and 66.7%, respectively. The test-retest and inter-observer agreement rates were both 95%. The K-MMSE scores and T&C Test were significantly related in the elderly from a rural community (p<0.01), The T&C Test was not influenced by the educational status. The Time and Change Tests took a mean of 6.3 and 12.7 seconds, respectively, to complete Conclusion : The T&C Test is a simple, accurate and reliable, performance-based tool in the screening for dementia. Because it is quick, and easy-to-use, it is hoped the T&C Test will be used for the widespread cognitive screening of aging populations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.882-890
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• 2009

In this paper, we describe a compensation method that can be used for the situation where Loran receivers lose their phase lock to the received Loran signals when Loran signals are employed for the synchronization of national infrastructures such as telecommunication networks, electric power distribution and so on. In losing the phase lock to the received signals in a Loran receiver, the inner oscillator of the receiver starts free-running and the performance of the timing synchronization signals which are locked to the oscillator's phase is very severly degraded, so the timing accuracy under 1 us for a Primary Reference Clock (PRC) required in the International Telecommunications Union (ITU) G.811 standard can not be satisfied in the situation. Therefore, in this paper, we propose a method which can compensate the phase jump by using a compensation algorithm when a Loran receiver loses its phase lock and the performance evaluation of the proposed algorithm is achieved by the Maximum Time Interval Error (MTIE) of the measured data. From the performance evaluation results, it is observed that the requirement under 1 us for a PRC can be easily achieved by using the proposed algorithm showing about 0.6 us with under 30 minutes mean interval of smoothing with 1 hour period when the loss of phase lock occurs.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• Journal of Radiation Protection and Research
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• v.6 no.1
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• pp.25-30
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• 1981

A measurement has been made for the radioactivities (or concentrations) of radon daughters, i.e., RaA, RaB and RaC in airborne dust by means of single filtering method. This is to evaluate the radioactivities in terms of Ci or WL (working level) from gross alpha counts measured in the selected-time intervals after an air sample is taken from a membrane filter paper with a mean pore size of $0.8{\mu}m$. This work involves determinations of standard deviation in radioactivities, radioactive equilibrium factor and ratio. It appears that a concentration of total radon daughters is $0.30{\sim}2.36pCi/l\;or\;0.89{\times}10^{-3}{\sim}6.57{\times}10^{-3}WL$, depending on the sampling time. Generally the highest concentration was observed around nine o'clock in a day while the lowest value was obtained around seventeen o'clock. Standard deviations based on counting statistics of RaA's, RaB's and RaC's concentrations are ${\pm}57.75%,\;{\pm}22.32%\;and\;{\pm}31.29%$, respectively. It is revealed that the radioactive equilibrium factor is 0.322 while the radioactive equilibrium ratio is of pattern $C_1>C_2>C_3$ in general. Here $C_1,\;C_2\;and\;C_3$ stand for concentrations of RaA,RaB and RaC, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.76-84
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• 2013

In the passive emitter localization using instantaneous TDOA (time difference of arrival) and FDOA (frequency difference of arrival) measurements, the estimation accuracy can be improved by collecting additional measurements. To achieve this goal, it is required to increase the number of the sensors. However, in electronic warfare environment, a large number of sensors cause the loss of military strength due to high probability of intercept. Also, the additional processes should be considered such as the data link and the clock synchronization between the sensors. Hence, in this paper, the passive localization of a stationary emitter is presented by using the successive TDOA and FDOA measurements from two moving sensors. In this case, since an independent pair of sensors is added in the data set at every instant of measurement, each pair of sensors does not share the common reference sensor. Therefore, the QCLS (quadratic correction least squares) methods cannot be applied, in which all pairs of sensor should include the common reference sensor. For this reason, a Gauss-Newton algorithm is adopted to solve the non-linear least square problem. In addition, to show the performance of the proposed method, we compare the RMSE (root mean square error) of the estimates with CRLB (Cramer-Rao lower bound) and derived the CEP (circular error probable) planes to analyze the expected estimation performance on the 2-dimensional space.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• Journal of Trauma and Injury
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• v.30 no.3
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• pp.75-79
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• 2017

Purpose: Although trauma is the most common cause of death under age 18, Korean national pediatric trauma data has lack of clinical data. This study is to prepare manpower resources, equipment, and make a correct policy decision on pediatric trauma victims Methods: The study enrolled 528 patients under age 16 with traumatic injury visited Wonju Severance Christian Hostpital Trauma Center, from February 12, 2015 to December 31, 2016. We analyzed the distribution of gender, age, place and time of the accident, injury mechanism, injury severity, and injured organ by medical record. Results: The major injury mechanisms were blunt injury in 485 (91.90%), penetrating injury in 27 (5.10%), burn in 13 (2.50%), near drowning in 2 (0.40%), and foreign body ingestion in 1 (0.20%). Ninety-seven (18.4%) patients were injured at home and 67 (12.7%) patients were injured at school. The overall mortality rate was 1.13% (n=6). 5 mortalities were related to automobile accident and one was fall down. Mean Injury Severity Score (ISS) was 4 (2, 8). No statistical significance was observed in the mean ISS between each age group. The peak time of accident occurrence was between 16 and 17 o'clock. The mean ISS was higher in blunt injury group than penetrating injury with statistical significance ($6.50{\pm}7.60$ vs. $3.00{\pm}8.10$; p<0.05). The most common injury site was upper extremity. Mean ISS was highest in thorax injury. However, mean ISS of thorax injury was higher with statistical significance only compared with face, neck and upper extremity injury. Conclusions: We reported our pediatric trauma patients data of our hospital level I trauma center, which is the only one level I trauma center of Gangwon Province. These data is useful to prevent and prepare for pediatric trauma.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.39-47
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• 1998

A fourth-order $\Sigma$-$\Delta$ modulator is designed and implemented in 0.6 $\mu\textrm{m}$ CMOS technology. The modulator is verified by introducing nonlinear factors such as DC gain and slew rate in system model that determines the transfer function in S-domain and in time-domain. Dynamic range is more than 110 dB and the peak SM is 102.6 dB at a clock rate of 2.8224 MHz for voiceband signal. The structure of a ∑-$\Delta$ modulator is a modified fourth-order ∑-$\Delta$ modulator using direct feedback loop method, which improves performance and consumes less power. The transmission zero for noise is located in the first-second integrator loop, which reduces entire size of capacitors, reduces the active area of the chip, improves the performance, and reduces power dissipation. The system is stable because the output variation with respect to unit time is small compared with that of the third integrator. It is easy to implement because the size of the capacitor in the first integrator, and the size of the third integrator is small because we use the noise reduction technique. This paper represents a new design method by modeling that conceptually decides transfer function in S-domain and in Z-domain, determines the cutoff frequency of signal, maximizes signal power in each integrator, and decides optimal transmission-zero frequency for noise. The active area of the prototype chip is 5.25$\textrm{mm}^2$, and it dissipates 10 mW of power from a 5V supply.

• Journal of KIISE:Databases
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• v.32 no.5
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• pp.473-486
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• 2005

The Hippocratic database model recently proposed by Agrawal et at. incorporates privacy protection capabilities into relational databases. The authors have subsequenty proposed the Hippocratic XML daかabase model[4], an extension of the Hippocratic database model for XML databases. In this paper, we propose a new concept that we cail the dynamic predicate(DP) for effective access control in the Hippocratic XML database model. A DP is a novel concept that represents a dynamically constructed rendition that tan be adapted for determining the accessibility of elements during query execution. DPs allow us to effectively integrate authorization checking into the query plan so that unauthorized elements are excluded in the process of query execution. Using synthetic and real data, we have performed extensive experiments comparing query processing time with those of existing access control mechanisms. The results show that the proposed access control mechanism improves the wall clock time by up to 219 times over the top-down access control strategy and by up to 499 times over the bottom-up access control strategy. The major contribution of our, paper is enabling effective integration of access control mechanisms with the query plan using the DP under the Hippocratic XML database model.