• Earthquakes and Structures
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• 제7권2호
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• pp.217-231
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• 2014

Ancient masonry towers are regarded as among the most important historical heritage structures of the world. These slender structures typically have orthogonal and circular geometry in plane. These structural forms are commonly installed with adjacent structures. Because of their geometrical shapes and structural constraints, ancient masonry towers are more vulnerable to earthquake damage. The main goal of the paper is to investigate the seismic behavior of Erzurum Clock Tower under earthquake loading and to determine the contribution of the castle walls to the seismic performance of the tower. In this study, four three-dimensional finite element models of the Erzurum Clock Tower were developed and the seismic responses of the models were investigated. Time history analyses were performed using the earthquakes that took place in Turkey in 1983 near Erzurum and in 1992 near Erzincan. In the first model, the clock tower was modeled without the adjacent walls; in the second model, the clock tower was modeled with a castle wall on the south side; in the third model, the clock tower was modeled with a castle wall on the north side; and in the last model, the clock tower was modeled with two castle walls on both the north and south sides. Results of the analyses show that the adjacent walls do not allow lateral movements and the horizontal displacements decreases. It is concluded that the adjacent structures should be taken into consideration when modeling seismic performance in order to get accurate and realistic results.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 추계종합학술대회
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• pp.593-599
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• 2007

PC based DVR이 점차 확산되고 있는 추세이다. 대부분의 DVR장치가 감시 및 보안업무에 이용되므로 정확한 시간정보제공이 필요하지만 여러 요인으로 인하여 정확한 시각을 유지하지 못하고 있는 실정이다. 정확한 시각정보를 제공하기 위해서는 부가장비를 통해 시각보정이 이루어 져야 한다. 경제성과 사용 환경 등을 고려하면 광역네트워크에 의존하지 않고서도 시각동기를 유지할 수 있는 GPS를 이용한 시스템이 가장 타당하다. 본 연구에서는 GPS의 시각 Data를 이용하여 PC Based DVR의 시스템시각을 정확하게 유지하는 시스템을 구현하고 실험을 통해 결과를 분석하기 위하여 1) GPS위성으로부터 시각정보를 수신하는 시각원 수신 모듈과 2) PC Based DVR에 제공하는 H/W Unit인 GPSW와 3) 이 장치와 통신하며 시각을 보정하는 Demon인 PCSW을 제작하여 PC시스템 시각을 UTC와 수ms 이내의 오차로 동기할 수 있도록 하고 결과를 측정하였다.

• Animal cells and systems
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• 제16권1호
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• pp.1-10
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• 2012

Most living organisms synchronize their physiological and behavioral activities with the daily changes in the environment using intrinsic time-keeping systems called circadian clocks. In mammals, the key molecular features of the internal clock are transcription- and translational-based negative feedback loops, in which clock-specific transcription factors activate the periodic expression of their own repressors, thereby generating the circadian rhythms. CLOCK and BMAL1, the basic helix-loop-helix (bHLH)/PAS transcription factors, constitute the positive limb of the molecular clock oscillator. Recent investigations have shown that various levels of posttranslational regulation work in concert with CLOCK/BMAL1 in mediating circadian and cellular stimuli to control and reset the circadian rhythmicity. Here we review how the CLOCK and BMAL1 activities are regulated by intracellular distribution, posttranslational modification, and the recruitment of various epigenetic regulators in response to circadian and cellular signaling pathways.

• 한국위성정보통신학회논문지
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• 제10권2호
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• pp.102-108
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• 2015

일반적으로 TDMA(Time Division Multiple Access)를 기반으로 하는 양방향 위성 통신 시스템에서는 중심국과 멀리 떨어진 단말국간의 네트워크 동기를 필요로 한다. 본 논문은 양방향 위성시스템을 위한 국제규격인 DVB-S2/RCS2에서 제시한 NCR(Network Clock Reference) 복원 구조를 기반으로 네트워크 클럭 동기에 대한 개념을 설명한다. 또한 DVB-S2에서 CCM(Constant Coding & Modulation) 운용 모드와 부호율, 변조방식을 바꿔 throughput을 최적화 하는 ACM(Adaptive Coding & Modulation) 운용 모드를 지원하는 새로운 NCR 삽입 구조를 제안하였으며 이에 대한 시뮬레이션을 통해 타당성을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• 한국통신학회논문지
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• 제32권7C호
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• pp.608-615
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• 2007

일반적으로 양방향 전송을 통한 TOA(Time Of Arrival) 정보는 두 디바이스간의 정확한 RTT(Round Trip Time) 정보로부터 도출되지만 디바이스간의 서로 다른 클럭 표류의 영향으로 인하여 RTT 측정 시 요구되는 응답 시간이 길 경우 매우 심각한 TOA 오차를 야기 시키게 된다. 이를 해결하기 위해서 본 논문에서는 비동기 시스템에서 클럭 표류의 영향을 줄이면서 TOA와 TDOA(Time Difference Of Arrival) 정보를 획득하는 방안을 제안한다. 이를 검증하기 위해서 IEEE 802.15.4a Task Group에서 제시한 단방향 전송을 통한 측위 방안과 비교하였으며 제안된 방안이 기존 방법들보다 개선된 성능을 보임을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• 한국항행학회논문지
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• 제18권5호
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• pp.429-436
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• 2014

본 논문에서는 의사위성과 GPS 위성 사이의 시각동기를 위한 세가지 동기 방안을 제안하고 시각동기 기법의 성능 분석에 필요한 의사위성 시각동기 오차요소에 대해 분석한다. 제시한 세가지 시각동기 방안으로는 의사위성 시각동기 스테이션 구축 방안, UTC(KRIS)의 시각정보원을 활용한 의사위성 시각동기 방안, GPS 시각용 수신기를 활용한 시각동기 방안이 있다. 또한 제안한 의사위성 시각동기 방안의 성능평가를 위한 시뮬레이션 구성을 위해 의사위성 시각동기 방안의 오차요소를 의사위성 및 기준 클럭의 오차, 전송선로에 의해 발생하는 오차, TIC에 의해 발생하는 오차, 클럭 동기 알고리즘에 의해 발생하는 오차로 구분하고 각 오차 요소를 분석하였다.

• Journal of Communications and Networks
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• 제18권1호
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• pp.65-74
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• 2016

Ship ad-hoc network (SANET) extends the coverage of the maritime communication among ships with the reduced cost. To fulfill the growing demands of real-time services, the SANET requires an efficient clock time synchronization algorithm which has not been carefully investigated under the ad-hoc maritime environment. This is mainly because the conventional algorithms only suggest to decrease the beacon collision probability that diminishes the clock drift among the units. However, the SANET is a very large-scale network in terms of geographic scope, e.g., with 100 km coverage. The key factor to affect the synchronization performance is the signal propagation delay, which has not being carefully considered in the existing algorithms. Therefore, it requires a robust multi-hop synchronization algorithm to support the communication among hundreds of the ships under the maritime environment. The proposed algorithm has to face and overcome several challenges, i.e., physical clock, e.g., coordinated universal time (UTC)/global positioning system (GPS) unavailable due to the atrocious weather, network link stability, and large propagation delay in the SANET. In this paper, we propose a logical clock synchronization algorithm with multi-hop function for the SANET, namely multi-hop clock synchronization for SANET (MCSS). It works in an ad-hoc manner in case of no UTC/GPS being available, and the multi-hop function makes sure the link stability of the network. For the proposed MCSS, the synchronization time reference nodes (STRNs) are efficiently selected by considering the propagation delay, and the beacon collision can be decreased by the combination of adaptive timing synchronization procedure (ATSP) with the proposed STRN selection procedure. Based on the simulation results, we finalize the multi-hop frame structure of the SANET by considering the clock synchronization, where the physical layer parameters are contrived to meet the requirements of target applications.

• 전자공학회논문지A
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• 제30A권7호
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• pp.75-81
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• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.