• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Journal of Engineering Education Research
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• v.5 no.1
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• pp.77-84
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• 2002

The 18th century Joseon(朝鮮) science philosopher Hong Dae-Yong(洪大容, 1731-83) tried to create his own scientific system, while partially keeping the Eastern view of nature and accepting Western science and technology. Most of all, he confirmed that Western science and technology was based on mathematical principles and accurate observation and wrote a math book, [Juhaesuyong(籌解需用)]. Therefore, we have good reason to call him a mathematician. He produced so many achievements that he can be considered a natural scientist in the late Joseon era; he accepted the Eastern view of nature critically and sometimes refused it. He also suggested new and various scientific thoughts, including an infinite universe theory, on the basis of Western scientific thought. Hong Dae-Yong emphasized the importance of practice. He understood the principle of the Western Honcheonui(渾天儀) and manufactured an alarm clock with a craftsman's help. He was an excellent engineer and he set a personal observatory. Considering the level of scientific technology at that time, it is reasonable to regard Hong Dae-Yong as a 'scientific technologist in the 18th century Joseonera', well equipped as a mathematician, a natural scientist, and an engineer. In conclusion, it is with 'mathematical thinking, creative conception, and practical activities' that Hong Dae-Yong maintained throughout his life that we can set a guide to produce excellent Korean scientific technologists and engineers in the 21st century.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.39-47
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• 1997

This paper presents a single board digital signal processing system which can perform two-dimensional (2-D) digital infinite impulse response (IIR) filtering in realtime. We have developed an architecture to provide not only the necessary computational power but also a balance of the system input/output and computational requirements. The architecture achieves large system throughput by using highly parallel processing at both the system and processor levels. It reduces system data communication requirements significantly by taking advantage of a custom-designed processor and by providing each processor with its own input and ouput channel. After system initialization, almost 100 percent of the time is used for data processing. Data transfers occur concurrently with data processing. The functional level simulation reveals that the system throughput can reach as high as one pixel per system cycle. With only 10MHz clock frequency system, it can implement up to fourth order 2-D IIR filters for video-rate data ($512\times512$ pixels per frame at 30 frames per second). If we increase the system frequency, the system can be used for the preprocessing and postprocessing of video signal of HDTV.

• Molecules and Cells
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• v.26 no.1
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• pp.53-60
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• 2008

We characterized the human endogenous retrovirus (HERV-W) family in humans and primates. In silico expression data indicated that 22 complete HERV-W families from human chromosomes 1-3, 5-8, 10-12, 15, 19, and X are randomly expressed in various tissues. Quantitative real-time RT-PCR analysis of the HERV-W env gene derived from human chromosome 7q21.2 indicated predominant expression in the human placenta. Several copies of repeat sequences (SINE, LINE, LTR, simple repeat) were detected within the complete or processed pseudo HERV-W of the human, chimpanzee, and rhesus monkey. Compared to other regions (5'LTR, Gag, Gag-Pol, Env, 3'LTR), the repeat family has been mainly integrated into the region spanning the 5'LTRs of Gag (1398 bp) and Pol (3242 bp). FISH detected the HERV-W probe (fosWE1) derived from a gorilla fosmid library in the metaphase chromosomes of all primates (five hominoids, three Old World monkeys, two New World monkeys, and one prosimian), but not in Tupaia. This finding was supported by molecular clock and phylogeny data using the divergence values of the complete HERV-W LTR elements. The data suggested that the HERV-W family was integrated into the primate genome approximately 63 million years (Myr) ago, and evolved independently during the course of primate radiation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.73-81
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• 2011

As high speed digital systems continue to use components with faster edge rate and clock speeds, transmission of the digital information, it can bring about many troubles. The increasing requirement for controlled impedance PCBs becomes both a critical success factor and a design challenge to implement a system. Especially, the noise sources in high frequency digital systems include the noise in power supply, ground and packaging, and they destroy the fidelity of signals. Therefore PCB design with impendence matching is needed to improve fidelity of signal in H/W. In this paper, we have developed an impedance control and analysis tool for multi-layer PCB design, and simulates the tracks controlled impedance with the test coupon. So, it can save the design time and support the economical PCB design.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.4
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• pp.247-252
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• 2009

This paper presents an Integer-N phase-locked loop (PLL) frequency synthesizer using a novel prescaler based on a charge pump and clock triggering circuit. A quadrature VCO has been designed for the 900MHz UHF RFID application. In this circuit, a voltage-controlled oscillator(VCO), a novel Prescaler, phase frequency detector(PFD), charge pump(CP), and analog lock detector(ALD) have been integrated with 0.35-${\mu}m$CMOS process. The integer divider has been developed with a verilog-HDL module, and the PLL mixed mode simulation has been performed with Spectre-Verilog co-simulator. The sweep range of VCO is designed from 828 to 960 MHz and the VCO generates four phase quadrature signals. The simulation results show that the phase noise of VCO is -102dBc/Hz at 100 KHz offset frequency, and the maximum lock-in time is about 4us with 32MHz step change (from 896 to 928 MHz).

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.385-390
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• 2017

Owing to the development of IT technology, a computerized system in various ways such as a variety of company's businesses, factory automation system and hospital healthcare system is introduced and operated. And it is possible to say that a computer system is more important than anything else to the extent that all businesses are suspended in case the system is down. Attention should be always paid to environmental management such as temperature, humidity and fire in server room for the normal operation of system in this situation. It is thought that there is necessity for a low-cost system which independently monitors environment round the clock in the situation where the person in charge doesn't pay attention and which informs a person in charge in real time when an event occurs for the operation of this small server room. Consequently, it is to be hoped that the suspension of service provided by computer system, which may occur due to a specific event, can be prevented.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.111-120
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• 2001

VC merging involves distinguishing cells from an identical merged VC label. Various approaches have been proposed to help this identification process. However, most of them incur additional buffering, protocol overhead and/or variable delay. They make the provision of QoS difficult to achieve. So it was proposed a merge capable scheduler to support VC-merging (VCMS). However, in situations where all VCs are to be merged or the incoming traffic load is very low, it could happen that there are not enough non-merging cells to snoop. In this situation the scheduler uses special control cells to fill the empty time slots out. Too many control cells can cause high cell loss ratio and an additional packet transfer delay. To overcome the drawbacks, we propose a Sequence Skipping(SS) method where the sequencers skip the empty queues and insert SS cells. We show SS method is suitable for VC-merging and can reduce the cell loss ratio and the mean packet transfer delay through simulations.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.109-114
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• 2004

This paper presents a high-speed bit-parallel systolic divider for computing modular division A($\chi$)/B($\chi$) mod G($\chi$) in finite fields GF$(2^m)$. The presented divider is based on the binary GCD algorithm and verified through FPGA implementation. The proposed architecture produces division results at a rate of one every 1 clock cycles after an initial delay of 5m-2. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. In addition, since the proposed architecture does not restrict the choice of irreducible polynomials and has regularity and modularity, it provides a high flexibility and Scalability with respect to the field size m. Therefore, the proposed divider is well suited to VLSI implementation.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.1-8
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• 2013

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.