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http://dx.doi.org/10.9708/jksci.2013.18.2.001

Cache memory system for high performance CPU with 4GHz  

Jung, Bo-Sung (Dept. of control and Instrumentation Engineering, Gyeongsang National University)
Lee, Jung-Hoon (Dept. of control and Instrumentation Engineering, Gyeongsang National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.18, no.2, 2013 , pp. 1-8 More about this Journal
Abstract
TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy $^*$ Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.
Keywords
Data cache memory; Dynamic access times; low power consumption;
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