• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.67-77
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• 2004

Value prediction is a technique to obtain performance gains by supplying earlier source values of its data dependent instructions using predicted value of a instruction. To fully exploit the potential of value speculation, however, the efficient recovery mechanism is necessary in case of value misprediction. In this paper, we propose a sequential and selective recovery mechanism for value misprediction. It searches data dependency chain of the mispredicted instruction sequentially without pipeline stalls and adverse impact on clock cycle time. In our scheme, only the dependent instructions on the predicted instruction is selectively squashed and reissued in case of value misprediction.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.56-65
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• 1999

This paper presents an architecture and its instruction set for a graphic coprocessor(GCP) which can be used for a multimedia server. The proposed instruction set employs parallel architecture concepts, such as SIMD and Superscalar. GCP consists of a scheduler and four functional units. The scheduler solves an instruction bottleneck problem causing by sharing with four general processors(GPs). GCP can execute up to 4 instructions in parallel. It consists of about 56,000 gates and operates at 30 MHz clock frequency due to speed limitation of SOG technology. GCP meets the real-time DCT algorithm requirement of the CIF image format and can process up to 63 frames/sec for the DCT Algorithm and 21 frames/sec for the Full Block matching Algorithm of the CIF image format.

• Journal of the Korean Society of Tobacco Science
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• v.22 no.2
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• pp.138-142
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• 2000

The effects of stalk cutting time and environmental factors such as air temperature, leaf temperature, solar radiation and leaf moisture content during harvesting and curing in burley tobacco(Nicotiana tabacum L.) on weight loss of fresh stalks and sunburning in leaves were investigated at Chonju Experiment Station, Korea Ginseng & Tobacco Research Institute in 1996 and 1997. Twelve to fifteen percent of the fresh weight was lost in 3 to 4 hours after stalk-cutting, and sunburned leaves could be observed in case of stalk cutting between 11:00 and 15:00 O'clock on a clear sunny day, when the air temperature was 34 to 35$^{\circ}C$, leaf temperature 52 to 54$^{\circ}C$, and solar radiation 700 to 940 w/$m^2$. The leaves exposed to this weather condition were sunburned within 1 hour after stalk cutting. But low temperature (below $25^{\circ}C$) with high solar radiation(above 700w/m2) or high temperature(above 3$0^{\circ}C$) with low solar radiation (below 600w$m^2$) did not induce the sunburn damage in leaves. As the leaf temperature and leaf moisture content were higher, the sunburned leaves increased. The leaves at the higher stalk position were more easily sunburned than those at the lower. This result indicates that the immature leaves with higher chlorophyll content might be more susceptible to sunburning.

• Convergence Security Journal
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• v.5 no.3
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• pp.23-32
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• 2005

This paper presents a 128-bit Reversible Cellular Automata (RCA) based lightweight block cipher for Ubiquitous computing security. To satisfy resource-constraints for Ubiquitous computing, it is designed as block architecture based on Cellular Automata with high pseudo-randomness. Our implementation requires 704 clock cycles and consumes 2,874 gates for encryption of a 128-bit data block. In conclusion, the processing time outperformed that of AES and NTRU by 31%, and the number of gate was saved by 20%. We evaluate robustness of our implementation against both Differential Cryptanalysis and Strict Avalanche Criterion.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2136-2149
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• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2435-2437
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• 2004

In this paper, an obstacle avoidance algorithm is proposed for a network-based robot considering network delay by distribution. The proposed algorithm is based on the VFH(Vector Field Histogram) algorithm, and for the network-based robot system, in which it is assumed robot localization information is transmitted through network communication. In this paper, target vector for the VFH algorithm is estimated through the robot localization information and the measurement of its delay by distribution. The delay measurement is performed by time-stamp method. To synchronize all local clocks of the nodes distributed on the network, a global clock synchronization method is adopted. With the delay measurement, the robot localization estimation is performed by calculating the kinematics of the robot. The validation of the proposed algorithm is performed through the performance comparison of the obstacle avoidance between the proposed algorithm and the existing VFH algorithm on the network-based autonomous mobile robot.

• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.

• Journal of the Korean Society of Costume
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• v.58 no.7
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• pp.119-132
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• 2008

This study intended to develop and produce a modern form of fashion design for the Korean creative dance performance, 'Crazy Skirt Collage', which expressed conflict between internal ego and a persona in a woman. The qualitative method was used to analyze literature review, internet search and visual data of historically important cases related to the theme. Based on the analysis, the fashion design of the dance performanre by Hwang Hee-Yeon that was actually staged on Towol Theater, one of the Seoul Arts Center, was produced. The results wire as follows; First, the study confirmed a change of persona that revealed a female's animus strongly as it moved into the modern time. Second, the female's persona was expressed through long skirts, slips, dress shoes, handbags, military shoes, dresses with long zippers, trousers, wedding dresses and Korean full skirts during the performance, while the female's animus through male coats, panties, big bags and clock. In conclusion, it is necessary to study new expressive methods, that is, dance clothes using advanced equipment such as lights, videos or other variety of materials. It is also important to understand aesthetics of modern women's ordinary lives and to adapt ordinary clothes to dance clothes in various methods in order to express their modern lives appropriately through Korean creative dance.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.17 no.5
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• pp.404-409
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• 2005

This study is to investigate effects of thermal conditions on sleep. Five female university students participated in the sleep experiment. Three temperature levels (22, 26, and $30^{\circ}C$) were given, and relative humidity was maintained to $50\%$. When as subject arrived in the chamber at 9 o'clock in the evening, questionnaire was given to check physical and psychological conditions. After checking conditions, subjects went to bed till 07 : 30 in the morning. Body movement was checked during sleeping. After sleep in the chamber, questionnaire was given to the subject in order to check sleep quality. Subjects evaluated sleep quality by themselves by answering the time they fall asleep and wake up, frequency of wake during sleep, causes of each waking, and feeling after sleep. Sleep quality was rated with 7-point scale. At $30^{\circ}C$ condition, body movement was significantly higher than of other thermal conditions. The best sleep quality was obtained at the $26^{\circ}C$ condition, while the worst sleep was taken at the $30^{\circ}C$ condition.