• Journal of Astronomy and Space Sciences
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• v.34 no.1
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• pp.19-30
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• 2017

The optical wide-field patrol network (OWL-Net) is a Korean optical surveillance system that tracks and monitors domestic satellites. In this study, a batch least squares algorithm was developed for optical measurements and verified by Monte Carlo simulation and covariance analysis. Potential error sources of OWL-Net, such as noise, bias, and clock errors, were analyzed. There is a linear relation between the estimation accuracy and the noise level, and the accuracy significantly depends on the declination bias. In addition, the time-tagging error significantly degrades the observation accuracy, while the time-synchronization offset corresponds to the orbital motion. The Cartesian state vector and measurement bias were determined using the OWL-Net tracking data of the KOMPSAT-1 and Cryosat-2 satellites. The comparison with known orbital information based on two-line elements (TLE) and the consolidated prediction format (CPF) shows that the orbit determination accuracy is similar to that of TLE. Furthermore, the precision and accuracy of OWL-Net observation data were determined to be tens of arcsec and sub-degree level, respectively.

• ETRI Journal
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• v.34 no.1
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• pp.17-23
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• 2012

This paper analyzes the feasibility of a new 3DTV broadcasting service scenario via Advanced Television Systems Committee Mobile/Handheld (ATSC-M/H). We suggest a dual-channel system in which a left-view image is encoded by MPEG-2 with HD quality and a small-sized right-view image is encoded by AVC. Also, the left view is transmitted through ATSC main channel and the right view is transmitted through ATSC-M/H channel. Although the transport stream formats of two channels are different from each other, we demonstrate that it is possible for the ATSC 2.0 decoder to synchronize the display of the left and right views when both encoders use a common wall clock and time stamp. We also propose a program specific information descriptor which guarantees full compatibility with the conventional 2D HDTV and emerging mobile TV services. Finally, we provide the results of subjective visual quality assessment of the proposed system in support of its 3DTV service quality.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.36-42
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• 2002

In this paper, we proposed a multiplicative algorithm for two polynomials with all non-zero coefficients over finite field GF($P^m$). Using the proposed multiplicative algorithm, we constructed the multiplier of modular architecture with parallel in-output. The proposed multiplier is composed of $(m+1)^2$ identical cells, each cell consists of one mod(p) additional gate and one mod(p) multiplicative gate. Proposed multiplier need one mod(p) multiplicative gate delay time and m mod(p) additional gate delay time not clock. Also, our architecture is regular and possesses the property of modularity, therefore well-suited for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.88-97
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• 2000

We have proposed and analysed a novel Lookup Algorithm which had a short switching speed and tiny memory size for IP router. This algorithm could simply be implemeted by a hardware with SRAM because of simple structure. This Lookup scheme needs 1${\sim}$3 memory access times. When we simulated with 40,000 routing record obtained from IPMA Website, the maximum memory size of this algorithm was 316KB(the offset threshold for compression algorithm was 8). When we simulated by HDL using ALTERA EPM7256 series and 100MHz clock and SRAM of 10ns access time, the total lookup time was 45ns for two memory access, 175ns for three memory access.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.430-442
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• 2013

This paper presents a fast multi-reference frame integer motion estimator for H.264/AVC. The proposed system uses the previously proposed fast multi-reference frame algorithm. The previously proposed algorithm executes a full search area motion estimation in reference frames 0 and 1. After that, the search areas of motion estimation in reference frames 2, 3 and 4 are minimized by a linear relationship between the motion vector and the distances from the current frame to the reference frames. For hardware implementation, the modified algorithm optimizes the search area, reduces the overlapping search area and modifies a division equation. Because the search area is reduced, the amount of computation is reduced by 58.7%. In experimental results, the modified algorithm shows an increase of bit-rate in 0.36% when compared with the five reference frame standard. The pipeline structure and the memory controller are also adopted for real-time video encoding. The proposed system is implemented using 0.13 um CMOS technology, and the gate count is 1089K with 6.50 KB of internal SRAM. It can encode a Full HD video ($1920{\times}1080P@30Hz$) in real-time at a 135 MHz clock speed with 5 reference frames.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.37-44
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• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.24 no.1
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• pp.1-6
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• 1988

For the purpose of making the detection range of fish detection system more longer and computerizing the system a parametric sound source, a timer and a digitizing circuit for the Apple II computer have been studied. The parametric sound of 5 KHz generated by passing AND gate two signals from carrier signal generator of 200KHz with modulator of 5KHz. This parametric acoustic source of 5KHz difference frequency had more higher directional resolution of 10 degrees than single frequency sound of 200KHz. Peripheral interface adaptor MC 6821 was adopted for interfacing to the Apple II personal computer. The timer consisted of six decade binary coded decimal counters (74 LS 190), and the digitizing circuit consisted of a sample and hold (LF 398) and an A/D converter(ADC 0808). The timer with 10KHz clock pulse had the measuring time from 0.1msec to 100sec. This time measuring range was satisfactory for the aim of the fish finding acoustic system.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.3103-3120
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• 2015

This paper presents a single-phase energy metering chip with built-in calibration function to measure electric power quantities. The entire chip consists of an analog front end, a filter block, a computation engine, a calibration engine, and an external interface block. The key design issues are how to reduce the implementation costs of the computation engine from repeatedly used arithmetic operations and how to simplify calibration procedure and reduce calibration time. The proposed energy metering chip simplifies the computation engine using time-division multiplexed arithmetic units. It also provides a simple and fast calibration scheme by using integrated digital calibration functionality. The chip is fabricated with 0.18-μm six-layer metal CMOS process and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4096 kHz and consumes 9.84 mW in 3.3 V supply.

• The Bulletin of The Korean Astronomical Society
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• v.41 no.1
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• pp.61.3-62
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• 2016

An asteroid family is a group of asteroidal objects in the proper orbital element space (a, e, and i), considered to have been produced by a disruption of a large parent body through a catastrophic collision. Family members usually have similar surface properties such as spectral taxonomy types, colors, and visible geometric albedo with a same dynamical age. Therefore an asteroid family could be called as a natural Solar System laboratory and is also regarded as a powerful tool to investigate space weathering and non-gravitational phenomena such as the Yarkovsky/YORP effects. We carry out time series photometric observations for a number of asteroid families to obtain their physical properties, including sizes, shapes, rotational periods, spin axes, colors, and H-G parameters based on nearly round-the-clock observations, using several 0.5-2 meter class telescopes in the Northern hemisphere, including BOAO 1.8 m, LOAO 1.0 m, SOAO 0.6 m facilities in KASI, McDonald Observatory 2.1 m instrument, NARIT 2.4 m and TUG 1.0 m telescopes. This study is expected to find, for the first time, some important clues on the collisional history in our Solar System and the mechanisms where the family members are being transported from the resonance regions in the Main-belt to the near Earth space.