• Earthquakes and Structures
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• v.7 no.2
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• pp.217-231
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• 2014

Ancient masonry towers are regarded as among the most important historical heritage structures of the world. These slender structures typically have orthogonal and circular geometry in plane. These structural forms are commonly installed with adjacent structures. Because of their geometrical shapes and structural constraints, ancient masonry towers are more vulnerable to earthquake damage. The main goal of the paper is to investigate the seismic behavior of Erzurum Clock Tower under earthquake loading and to determine the contribution of the castle walls to the seismic performance of the tower. In this study, four three-dimensional finite element models of the Erzurum Clock Tower were developed and the seismic responses of the models were investigated. Time history analyses were performed using the earthquakes that took place in Turkey in 1983 near Erzurum and in 1992 near Erzincan. In the first model, the clock tower was modeled without the adjacent walls; in the second model, the clock tower was modeled with a castle wall on the south side; in the third model, the clock tower was modeled with a castle wall on the north side; and in the last model, the clock tower was modeled with two castle walls on both the north and south sides. Results of the analyses show that the adjacent walls do not allow lateral movements and the horizontal displacements decreases. It is concluded that the adjacent structures should be taken into consideration when modeling seismic performance in order to get accurate and realistic results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.593-599
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• 2007

PC based DVR replaces existing analog CCTV system therefore expands the field and DVR is used for monitoring and security so it requires exact time(clock). But DVR system can't maintains exact clock causing several reasons. For providing exact time information we should use additional system. For economical and usable environment, using GPS system is most suitable suggested solution than use WAN(Wide Area Network). Therefore in this paper for analysis the result of PC based DVR's system clock using GPS system, 1) clock source receiving module that receives the clock form GPS satellite and 2) GPSW H/W units that provide clock source to PC Based DVR 3)Daemon software named PCSW which adjust PC's clock so system could reduced the clock difference with UTC clock and measured the result.

• Animal cells and systems
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• v.16 no.1
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• pp.1-10
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• 2012

Most living organisms synchronize their physiological and behavioral activities with the daily changes in the environment using intrinsic time-keeping systems called circadian clocks. In mammals, the key molecular features of the internal clock are transcription- and translational-based negative feedback loops, in which clock-specific transcription factors activate the periodic expression of their own repressors, thereby generating the circadian rhythms. CLOCK and BMAL1, the basic helix-loop-helix (bHLH)/PAS transcription factors, constitute the positive limb of the molecular clock oscillator. Recent investigations have shown that various levels of posttranslational regulation work in concert with CLOCK/BMAL1 in mediating circadian and cellular stimuli to control and reset the circadian rhythmicity. Here we review how the CLOCK and BMAL1 activities are regulated by intracellular distribution, posttranslational modification, and the recruitment of various epigenetic regulators in response to circadian and cellular signaling pathways.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.102-108
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• 2015

In general, two way satellite communication systems based on TDMA(Time Division Multiple Access) require network clock synchronization between hub station and remote terminals. This paper describes basic concepts for network clock synchronization based on NCR(Network Clock Reference) clock recovery scheme as suggested in DVB-S2/ RCS2 international standards. in addition, a new NCR insertion method has been proposed and evaluated in terms of supporting CCM mode as well as ACM mode which optimizes throughput by changing code rates and modulation types ranging from QPSK to 32-APSK.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.608-615
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• 2007

Generally time of arrival (TOA) information via two way communications can be derived by accurate round trip time (RTT) between two devices. However, response time demanded in RTT measurement is long, a serious TOA error is caused by each different clock drift between two devices. In order to solve this problem, we propose the TOA and time difference of arrival (TDOA) estimation scheme with mitigating clock drift effect. To verify the performance of proposed method, we compared the proposed scheme with one way based TDOA acquisition method introduced by IEEE 802.15.4a Task Group and then we could conclude that the proposed method has better performance over other methods.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.515-520
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• 1998

In this paper, we propose a new fault tolerant architecture for high availability systems, where for module internal operations both processor modules perform the same tasks at the same time independently of each other while for module external operations both processor modules act actively. That is, operations of synchronization between dual processor modules except clock synchronization are requested only when module external operations are executed. The architecture can not only improve system availability by reducing system reintegration time but also reduce performance degradation problem due to frequent synchronization between dual processor modules. The clock unit consists of a clock generator and a clock synchronization circuit. This supplies a stable clock signal under clock unit disorder of any processor module or rapid clock signal variation. And this architecture achieves system availability and data credibility by designing as symmetrical form.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

• Journal of Communications and Networks
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• v.18 no.1
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• pp.65-74
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• 2016

Ship ad-hoc network (SANET) extends the coverage of the maritime communication among ships with the reduced cost. To fulfill the growing demands of real-time services, the SANET requires an efficient clock time synchronization algorithm which has not been carefully investigated under the ad-hoc maritime environment. This is mainly because the conventional algorithms only suggest to decrease the beacon collision probability that diminishes the clock drift among the units. However, the SANET is a very large-scale network in terms of geographic scope, e.g., with 100 km coverage. The key factor to affect the synchronization performance is the signal propagation delay, which has not being carefully considered in the existing algorithms. Therefore, it requires a robust multi-hop synchronization algorithm to support the communication among hundreds of the ships under the maritime environment. The proposed algorithm has to face and overcome several challenges, i.e., physical clock, e.g., coordinated universal time (UTC)/global positioning system (GPS) unavailable due to the atrocious weather, network link stability, and large propagation delay in the SANET. In this paper, we propose a logical clock synchronization algorithm with multi-hop function for the SANET, namely multi-hop clock synchronization for SANET (MCSS). It works in an ad-hoc manner in case of no UTC/GPS being available, and the multi-hop function makes sure the link stability of the network. For the proposed MCSS, the synchronization time reference nodes (STRNs) are efficiently selected by considering the propagation delay, and the beacon collision can be decreased by the combination of adaptive timing synchronization procedure (ATSP) with the proposed STRN selection procedure. Based on the simulation results, we finalize the multi-hop frame structure of the SANET by considering the clock synchronization, where the physical layer parameters are contrived to meet the requirements of target applications.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.75-81
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• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.