• Title/Summary/Keyword: throughput per cell

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Proposal and Evaluation of Ultra High Speed Wireless Cell Backbone Networks (도시형 초고속 무선통신 셀백본망의 제안 및 평가)

  • Shin, Cheon-Woo;Park, Sung-Hyun
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.243-248
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    • 2003
  • This paper is contents on that construct ultra high speed wireless communication cell backbone net of city using of wireless communication transceiver for millimeter wave band. A new type of 60GHz wave band wireless transceiver using NRD waveguide. This 60GHz transceiver has excellent signal's absorption characteristics of oxygen molecule than the other millimeter wave bands. We constructed service networks to cell interval within about 500m to 3Km laying stress on wireless backbone node using 60GHz transceivers, and did it so that city type wireless communication cell backbone networks of 155.52Mbps ATM(OC-3) may be possible. The possible use of wireless backbone networks technology in a rainy day and a clear day was evaluated at 1Km data link distance. We can measured bit error rate(BER). BER is $10^{-11}$ at 155.52Mbps ATM(OC-3) in a clear day and $10^{-6}$ in a heavy rain more than 35mm per time. Also, we constructed wireless cell backbone networks distance to use several 60GHz transceivers and investigated data transmission rate between main center and local center of long distance. In proposed wireless cell backbone networks, the data throughput was approximately 80Mbit/sec. Therefore, if use transceiver, it is possible that city type ultra high speed wireless communication cell backbone networks construction of 100Mbps, 155.52Mbps, 622Mbps, 1Gbps and 1.2Gbps degrees.

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Sub-channel Allocation Based on Multi-level Priority in OFDMA Systems

  • Lee, JongChan;Lee, MoonHo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.8
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    • pp.1876-1889
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    • 2013
  • Packet-based mobile multimedia services for the Internet differ with respect to their resource requirements, performance objectives, and resource usage efficiencies. Nonetheless, each mobile terminal should support a variety of multimedia services, sometimes even simultaneously. This paper proposes a sub-channel allocation scheme based on multi-level priority for supporting mobile multimedia services in an Orthogonal Frequency Division Multiple Access (OFDMA) system. We attempt to optimize the system for satisfying the Quality of Service (QoS) requirements of users and maximize the capacity of the system at the same time. In order to achieve this goal, the proposed scheme considers the Signal-to-Interference-plus-Noise Ratio (SINR) of co-sub-channels in adjacent cells, the Signal-to-Noise Ratio (SNR) grade of each sub-channel in the local cell on a per-user basis, and the characteristics of the individual services before allocating sub-channels. We used a simulation to evaluate our scheme with the performance measure of the outage probabilities, delays, and throughput.

Beamforming Optimization for Multiuser Two-Tier Networks

  • Jeong, Young-Min;Quek, Tony Q.S.;Shin, Hyun-Dong
    • Journal of Communications and Networks
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    • v.13 no.4
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    • pp.327-338
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    • 2011
  • With the incitation to reduce power consumption and the aggressive reuse of spectral resources, there is an inevitable trend towards the deployment of small-cell networks by decomposing a traditional single-tier network into a multi-tier network with very high throughput per network area. However, this cell size reduction increases the complexity of network operation and the severity of cross-tier interference. In this paper, we consider a downlink two-tier network comprising of a multiple-antenna macrocell base station and a single femtocell access point, each serving multiples users with a single antenna. In this scenario, we treat the following beamforming optimization problems: i) Total transmit power minimization problem; ii) mean-square error balancing problem; and iii) interference power minimization problem. In the presence of perfect channel state information (CSI), we formulate the optimization algorithms in a centralized manner and determine the optimal beamformers using standard convex optimization techniques. In addition, we propose semi-decentralized algorithms to overcome the drawback of centralized design by introducing the signal-to-leakage plus noise ratio criteria. Taking into account imperfect CSI for both centralized and semi-decentralized approaches, we also propose robust algorithms tailored by the worst-case design to mitigate the effect of channel uncertainty. Finally, numerical results are presented to validate our proposed algorithms.

A Grouped Input Buffered ATM switch for the HOL Blocking (HOL 블록킹을 위한 그룹형 입력버퍼 ATM 스위치)

  • Kim, Choong-Hun;Son, Yoo-Ek
    • The KIPS Transactions:PartC
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    • v.10C no.4
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    • pp.485-492
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    • 2003
  • This paper presents a new modified input buffered switch, which called a grouped input buffered (GIB) switch, to eliminate the influence of HOL blocking when using multiple input buffers in ATM switches. The GIB switch consists of grouped sub switches per a network stage. The switch gives extra paths and buffered switching elements between groups for transferring the blocked cells. As the result, the proposed model can reduce the effect by the HOL blocking and thereafter it enhances the performance of the switch. The simulation results show that the proposed scheme has good performance in comparison with previous works by using the parameters such as throughput, cell loss, delay and system power.

Application of Regularized Linear Regression Models Using Public Domain data for Cycle Life Prediction of Commercial Lithium-Ion Batteries (상업용 리튬 배터리의 수명 예측을 위한 고속대량충방전 데이터 정규화 선형회귀모델의 적용)

  • KIM, JANG-GOON;LEE, JONG-SOOK
    • Transactions of the Korean hydrogen and new energy society
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    • v.32 no.6
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    • pp.592-611
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    • 2021
  • In this study a rarely available high-throughput cycling data set of 124 commercial lithium iron phosphate/graphite cells cycled under fast-charging conditions, with widely varying cycle lives ranging from 150 to 2,300 cycles including in-cycle temperature and per-cycle IR measurements. We worked out own Python codes which reproduced the various data plots and machine learning approaches for cycle life prediction using early cycles and more details not presented in the article and the supplementary information. Particularly, we applied regularized ridge, lasso and elastic net linear regression models using features extracted from capacity fade curves, discharge voltage curves, and other data such as internal resistance and cell can temperature. We found that due to the limitation in the quantity and quality of the data from costly and lengthy battery testing a careful hyperparameter tuning may be required and that model features need to be extracted based on the domain knowledge.

A 4-parallel Scheduling Architecture for High-performance H.264/AVC Deblocking Filter (고성능 H.264/AVC 디블로킹 필터를 위한 4-병렬 스케줄링 아키텍처)

  • Ko, Byung-Soo;Kong, Jin-Hyeung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.8
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    • pp.63-72
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    • 2012
  • In this paper, we proposed a parallel architecture of line & block edge filter for high-performance H.264/AVC deblocking filter for Quad Full High Definition(Quad FHD) video real time processing. To improve throughput, we designed 4-parallel block edge filter with 16 line edge filter. To reduce internal buffer size and processing cycle, we scheduled 4-parallel zig-zag scan order as deblocking filtering order. To avoid data conflicts we placed 1 delay cycle between block edge filtering. We implemented interleaving buffer, as internal buffer of block edge filter, to sharing buffer for reducing buffer size. The proposed architecture was simulated in 0.18um standard cell library. The maximum operation frequency is 108MHz. The gate count is 140.16Kgates. The proposed H.264/AVC deblocking filter can support Quad FHD at 113.17 frames per second by running at 90MHz.

Design of H.264/AVC CABAC Encoder with an Efficient Storage Reduction of Syntax Elements (구문 요소의 저장 공간을 효과적으로 줄인 H.264/AVC CABAC 부호화기 설계)

  • Kim, Yoon-Sup;Moon, Jeon-Hak;Lee, Seong-Soo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.34-40
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    • 2010
  • This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

Real-time Disparity Acquisition Algorithm from Stereoscopic Image and its Hardware Implementation (스테레오 영상으로부터의 실시간 변이정보 획득 알고리듬 및 하드웨어 구현)

  • Shin, Wan-Soo;Choi, Hyun-Jun;Seo, Young-Ho;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.11C
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    • pp.1029-1039
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    • 2009
  • In this paper, the existing disparity aquisition algorithms were analyzed, on the bases of which a disparity generation technique that is superior in accuracy to the generation time was proposed. Basically it uses a pixel-by-pixel motion estimation technique. It has a merit of possibility of a high-speed operation. But the motion estimation technique has a disadvantage of lower accuracy because it depends on the similarity of the matching window regardless of the distribution characteristics of the texture in an image. Therefore, an enhanced technique to increase the accuracy of the disparity is required. This paper introduced a variable-sized window matching technique for this requirement. By the proposed technique, high accuracies could be obtained at the homogeneous regions and the object edges. A hardware to generate disparity image was designed, which was optimized to the processing speed so that a high throughput is possible. The hardware was designed by Verilog-HDL and synthesized using Hynix $0.35{\mu}m$ CMOS cell library. The designed hardware was operated stably at 120MHz using Cadence NC-VerilogTM and could process 15 frames per second at this clock frequency.

A Bio-inspired Hybrid Cross-Layer Routing Protocol for Energy Preservation in WSN-Assisted IoT

  • Tandon, Aditya;Kumar, Pramod;Rishiwal, Vinay;Yadav, Mano;Yadav, Preeti
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.4
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    • pp.1317-1341
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    • 2021
  • Nowadays, the Internet of Things (IoT) is adopted to enable effective and smooth communication among different networks. In some specific application, the Wireless Sensor Networks (WSN) are used in IoT to gather peculiar data without the interaction of human. The WSNs are self-organizing in nature, so it mostly prefer multi-hop data forwarding. Thus to achieve better communication, a cross-layer routing strategy is preferred. In the cross-layer routing strategy, the routing processed through three layers such as transport, data link, and physical layer. Even though effective communication achieved via a cross-layer routing strategy, energy is another constraint in WSN assisted IoT. Cluster-based communication is one of the most used strategies for effectively preserving energy in WSN routing. This paper proposes a Bio-inspired cross-layer routing (BiHCLR) protocol to achieve effective and energy preserving routing in WSN assisted IoT. Initially, the deployed sensor nodes are arranged in the form of a grid as per the grid-based routing strategy. Then to enable energy preservation in BiHCLR, the fuzzy logic approach is executed to select the Cluster Head (CH) for every cell of the grid. Then a hybrid bio-inspired algorithm is used to select the routing path. The hybrid algorithm combines moth search and Salp Swarm optimization techniques. The performance of the proposed BiHCLR is evaluated based on the Quality of Service (QoS) analysis in terms of Packet loss, error bit rate, transmission delay, lifetime of network, buffer occupancy and throughput. Then these performances are validated based on comparison with conventional routing strategies like Fuzzy-rule-based Energy Efficient Clustering and Immune-Inspired Routing (FEEC-IIR), Neuro-Fuzzy- Emperor Penguin Optimization (NF-EPO), Fuzzy Reinforcement Learning-based Data Gathering (FRLDG) and Hierarchical Energy Efficient Data gathering (HEED). Ultimately the performance of the proposed BiHCLR outperforms all other conventional techniques.

A Design of Fractional Motion Estimation Engine with 4×4 Block Unit of Interpolator & SAD Tree for 8K UHD H.264/AVC Encoder (8K UHD(7680×4320) H.264/AVC 부호화기를 위한 4×4블럭단위 보간 필터 및 SAD트리 기반 부화소 움직임 추정 엔진 설계)

  • Lee, Kyung-Ho;Kong, Jin-Hyeung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.6
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    • pp.145-155
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    • 2013
  • In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Fractional Motion Estimation in 8K UHD($7680{\times}4320$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $10{\times}10$ reference data for interpolation, we design 2D cache buffer which consists of the $10{\times}10$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The gate count is 436.5Kgates. The proposed H.264/AVC Fractional Motion Estimation can support 8K UHD at 30 frames per second by running at 187MHz.