• Mass Spectrometry Letters
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• v.12 no.2
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• pp.47-52
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• 2021

Evaluating the impurity concentrations in semiconductor thin films using time of flight secondary ion mass spectrometry (ToF-SIMS) is an effective technique. The mass interference between isotopes and matrix element in data interpretation makes the process complex. In this study, we have investigated the doping concentration of phosphorus in, phosphorus doped silicon thin film on glass using ToF-SIMS in the dynamic mode of operation. To overcome the mass interference between phosphorus and silicon isotopes, the quantitative analysis of counts to concentration conversion was done following two routes, standard relative sensitivity factor (RSF) and SIMetric software estimation. Phosphorus doped silicon thin film of 180 nm was grown on glass substrate using hot wire chemical vapor deposition technique for possible applications in optoelectronic devices. Using ToF-SIMS, the phosphorus-31 isotopes were detected in the range of 10¹~10⁴ counts. The silicon isotopes matrix element was measured from p-type silicon wafer from a separate measurement to avoid mass interference. For the both procedures, the phosphorus concentration versus depth profiles were plotted which agree with a percent difference of about 3% at 100 nm depth. The concentration of phosphorus in silicon was determined in the range of 10¹⁹~10²¹ atoms/cm³. The technique will be useful for estimating distributions of various dopants in the silicon thin film grown on glass using ToF-SIMS overcoming the mass interference between isotopes.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.194-194
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• 2003

As a result of the recent miniaturization an enhancement in the performance of thin film inductors and thin film transformers, there are increased demands for the thin films with high magnetic permeability in the high frequency range, high saturation magnetization, in high electrical resistivity, and low coercive force. In order to improve high frequency properties, we will investigate anisotropy field by shape and size of pattern. The Fe-Al-O thin films of 16mm and 1 $\mu\textrm{m}$ thickness were deposited on Si wafer, using RF magnetron reactive sputtering technique with the mixture of argon and oxygen gases. The fabricating conditions are obtained in the working partial pressure of 2mTorr, O$_2$ partial pressure of 5%, input power of 400W, and Al pellets on an Fe disk with purity of 99,9%. Magnetic properties of the continuous films as followed: the 4$\pi$M$\_$s/ of 19.4kG, H$\_$c/ of 0.6Oe, H$\_$k/ of 6.0Oe and effective permeability of 2500 up to 100㎒ were obtained. In this work, we expect to enhance effect of magnetic anisotropy on patterned of Fe-Al-O thin films.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.743-746
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• 2003

We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p$^{+}$Ge/p$^{+}$Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$, the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.3
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• pp.401-407
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• 2012

The recent manufacturing process in the thin wafers and flat panel necessitate new approaches to reduce handling fragile and surface-sensitive damage of components. This paper presents a new pneumatic levitation for non-contact handling of parts and substrates. This levitation can achieve non-contact handling by blowing air into an air pressure pick-up head with radial passages to generate a negative pressure region. Negative pressure is caused by the radial air flow by nozzle throat and through holes connecting to the bottom region. The numerical analysis deals with the levitational motion with different design factors. The dynamic motion is examined in terms of force balance(dynamic equilibrium) occurring to the flow field between two objects. The stable equilibrium position and the safe separation distance are determined by analyzing the local pressure distribution in the fluid motion. They make considerable design factors consisting the air pressure pick-up head. As a result, in case that the safe separation distance is beyond 0.7mm, the proposed pick-up head can levitate stably at the equilibrium position. Furthermore, it can provide little effect of torque, and obtain more wide picking region according to the head size.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2501-2503
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PTO layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PTO layer of c-axial orientation raised thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PTO layer were measured, too.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.39-44
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• 1997

Bulk type radiation detector of Au/Cd$_{1-x}$ Zn$_{x}$Te(x=20%)/Au structure using Cd$_{1-x}$ Zn$_{x}$Te(x=20%) wafer(3x4xl mm$^{3}$) grown by high pressure Bridgman method has been developed. We etched wafer surfaces with 2% Br-methanol solution and coated gold thin film on the surfaces by electroless deposition method for 5 min. in 49/o HAuCI$_{3}$ 4H20 solution. Initial etch rates of Cd, Zn and Te were 46%, 12% and 42% respectively. After etched, the surface of wafer was slightly revealed to Te rich condition. The leakage current was increased with etch time, but it didn't exceed 3nA at 50volt. The thickness of Au film was about 100nm by Rutherford Backscattering Spectroscopy(RBS). The resolution were 6.7% for 22.1 keV photon from 109 $^{109}$ Cd and 8.2% for 59.5 keV photon from $^{241}$ Am. The radiation detector such as Au/Cd$_{1-x}$ Zn$_{x}$Te(x=20%)/Au structure was more effective to monitor the low energy gamma radiation.iation.

• Design & Manufacturing
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• v.14 no.4
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• pp.58-64
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• 2020

Lately, the development of the semiconductor industry has led to the miniaturization of electronic devices. Therefore, semiconductor wafers of very thin thickness that can be used in Multi-Chip Packages are required. There is active research on the backgrinding process to reduce the thickness of the wafer. The backgrinding process polishes the backside of the wafer, reducing the thickness of the wafer to tens of ㎛. The equipment that performs the backgrinding process requires ultra-precision. Currently, there is no full auto backgrinding equipment in Korea. Therefore, in this study, ultra-precision backgrinding equipment was designed. In addition, finite element analysis was conducted to verify the equipment design validity. The deflection and structural stability of the backgrinding equipment were analyzed using finite element analysis.

• Design & Manufacturing
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• v.18 no.2
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• pp.9-16
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• 2024

Recently, there has been extensive research conducted on the miniaturization of semiconductors and the improvement of their integration to achieve high-quality and high-performance electronic devices. To integrate and miniaturize multiple semiconductors, thin and precise wafers are essential. The backgrinding process, which involves high-precision processing, is necessary to achieve this. The backgrinding system is used to grind and polish the back side of the wafer to reduce its thickness to ㎛ units. This enables the high integration and miniaturization of semiconductors and a flattening process to allow for detailed circuit design, ultimately leading to the production of IC chips. As the backgrinding system performs precision processing at the ㎛ unit, it is crucial to determine the stability of the equipment's rigidity. Additionally, the flatness and surface roughness of the processed wafer must be checked to confirm the processability of the backgrinding system. IIn this paper, the goal is to verify the processability of the back grinding system by analyzing the natural frequency and resonance frequency of the equipment through computer simulation and measuring and analyzing the flatness and surface roughness of wafers processed with backgrinding system. It was confirmed whether processing damage occurred due to vibration during the backgrinding process.