• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.15-15
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• 2008

산화물 반도체가 실리콘 기반의 기술을 대체할 새로운 기술로써 주목을 받기 시작하면서, 산화아연을 이용한 박막트랜지스터가 많은 주목을 받고 있다. 여기에 기존의 $SiO_2$를 대체할 새로운 High-k Material에 대한 연구 또한 진행되고 있는데, 이들의 가장 큰 문제점중 하나는 Interface Charge Trap이며, 그에 따른 결과로 히스테리시스 특성이 나타나게 되고, 이는 소자의 신뢰성에 큰 걸림돌이 되고 있다. 이번 연구에서는, High-k Material들 중의 하나인, $HfO_2$를 게이트 절연막으로 사용함에 있어서 Interface Charge Trap이 발생하는 문제를 해결하고자 하며, Low-k Material중에서 비교적 높은 유전상수를 갖는 $Al_2O_3$를 Buffer Layer로써 사용하여, 히스테리시스 특성을 향상 시켰다.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.524-526
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• 2009

The effects of In and Ga contents on characteristics of InGaZnO (IGZO) films grown by a sol-gel method and their thin film transistors (TFTs) have been investigated. Excess In incorporation into IGZO enhances the field effect mobilities of the TFTs due to the increase in conducting path ways, and decreases the grain size and the surface roughness of the films because more $InO_2^-$ ions induce cubic stacking faults with IGZO. Ga incorporation into results in decrease in carrier concentration of films and off-current of TFTs since Ga ion forms stronger chemical bonds with oxygen than Zn and In ions, acting as a carrier killer.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.318-321
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• 2009

We have studied transparent top gate Al-Zn-Sn-O (AZTO) TFTs with an $Al_2O_3$ protective layer (PL) on an active layer. We also fabricated a transparent 2.5 inch QCIF+AMOLED display panel using the AZTO TFT back-plane. The AZTO active layers were deposited by RF magnetron sputtering at room temperature and the PL was deposited by ALD with two different processes. The mobility and subthreshold slope were superior in the cases of the vacuum annealing and the oxygen plasma PL compared to the $O_2$ annealing and the water vapor PL, however, the bias stability was excellent for the TFTs of the $O_2$ annealing and the water vapor PL.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.889-892
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• 2009

We have developed a practical printing technology for the gate electrode of organic thin film transistors(OTFTs) by combining screen-printing with wet-etching process using nano-silver ink as a conducting material. The screen-printed and wet-etched Ag electrode exhibited a minimum line width of ~5 um, the thickness of ~65 nm, and a resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, producing good geometrical and electrical characteristics for gate electrode. The OTFTs with the screen-printed and wet-etched Ag electrode produced the saturation mobility of $0.13cm^2$/Vs and current on/off ratio of $1.79{\times}10^6$, being comparable to those of OTFT with the thermally evaporated Al gate electrode.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.550-552
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• 2009

The negative bias temperature instability on LTPS TFTs in a darkened and an illuminated environment was investigated. Experimental results reveal that the generation of interface state density showed no change between the different NBTI stresses. The degradation of the grain boundary trap under illumination was more significant than for the darkened environment.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.745-748
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• 2007

Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) were fabricated on a flexible metal substrate at $150\;^{\circ}C$. To increase the stability of the flexible a-Si:H TFTs, they were thermally annealed at $230\;^{\circ}C$. The field effect mobility was reduced because of the strain in a- Si:H TFT under thermal annealing.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.833-836
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• 2007

A low power and small area source driver using LTPS TFTs is proposed for mobile applications. This source driver adopts level shifter with holding latch function and new R-to-R type digital-to-analog converter (DAC). The power consumption and layout area of the proposed source driver are reduced by 23% and 25% for 16M colors and qVGA AM-OLED panel, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.257-260
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• 2007

Hydrogenated amorphous silicon thin film transistors were fabricated on a flexible metal substrate. A negative voltage at a floated gate can be induced by a negative substrate bias through a capacitor between the substrate and gate electrode. This can recover the shifted-threshold voltage to an original value.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.613-616
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• 1999

An active-matrix LCD using thin film transistors (TFTs)has been widely recognized as having potential for high-quality color flat-panel displays. Pixel-Design Array Simulation Tool (PDAST) was used to profoundly understand the gate signal distortion and pixel charging capability, which are the most critical limiting factors for high-quality TFT-LCDs. Since PDAST can simulate the gate data and pixel voltages of a certain pixel on TFT array at any time and at any location on an array, the effect of the new set of capacitance models on the pixel operations can be effectively analyzed, The set of models which is adopted from VLSI interconnections calculate more precise capacitance. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Journal of IKEEE
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• v.20 no.3
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• pp.330-332
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• 2016

In this study, we investigate the influence of channel length of bendable a-Si:H thin film transistors (TFTs) on their electrical characteristics as a function of bending strain. Under a tensile strain of 1.69%, $8{\mu}m$-channel-length TFT has the threshold voltage shift up to 5.25 V, while $100{\mu}m$-channel-length TFT operates stably.