• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.618-618
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• 2013

Graphene is only one atom thick planar sheet of sp2-bonded carbon atoms arranged in a honeycomb crystal lattice, which has flexible and transparent characteristics with extremely high mobility. These noteworthy properties of graphene have given various applicable opportunities as electrode and/or channel for various flexible devices via suitable physical and chemical modifications. In this work, for the development of all-graphene devices, we performed to synthesize alternately patterned structure of mono- and multi-layer graphene by using the patterned Ni film on Cu foil, having much different carbon solid solubilities. Depending on the process temperature, Ni film thickness, introducing occasion of methane and gas ratio of CH4/H2, the thickness and width of the multi-layer graphene were considerably changed, while the formation of monolayer graphene on just Cu foil was not seriously influenced. Based on the alternately patterned structure of mono- and multi-layer graphene as a channel and electrode, respectively, the flexible TFT (thin film transistor) on SiO2/Si substrate was fabricated by simple transfer and O2 plasma etching process, and the I-V characteristics were measured. As comparing the change of resistance for bending radius and the stability for a various number of repeated bending, we could confirm that multi-layer graphene electrode is better than Au/Ti electrode for flexible applications.

• International Journal of Precision Engineering and Manufacturing
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• v.7 no.1
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• pp.51-56
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• 2006

A computer code was developed to simulate both the thermal stresses introduced during the post-filling stage and the in-plane deformation after ejection process by finite element method based on the plane stress theory. The computer simulation was applied to the mold design of a 2 inch light guide plate (LGP) for thin film transistor (TFT)-liquid crystal displays (LCD). With injection molding experiments based on the design of experiments (DOE) technique, the influences of the processing conditions in injection molding on brightness and uniformity of the LGP were investigated, and the optimal processing parameters were selected to increase the brightness and uniformity. The verification experiment showed that the brightness and uniformity of the LGP were increased dramatically under the selected optimal processing conditions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.8-8
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• 2009

Thin-film transistors (TFTs) were fabricated using amorphous indium gallium zinc oxide (a-IGZO) channels by rf-magnetron sputtering at room temperature. We have studied the effect of oxygen partial pressure on the threshold voltage($V_{th}$) of a-IGZO TFTs. Interestingly, the $V_{th}$ value of the oxide TFTs are slightly shifted in the positive direction due to increasing $O_2$ ratio from 1.2 to 1.8%. The device performance is significantly affected by varying $O_2$ ratio, which is closely related with oxygen vacancies provide the needed free carriers for electrical conduction.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.166-171
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• 2016

Nickel silicide is main issue in Polycrystalline silicon Thin Film Transistor (TFT) which is made by Metal Induced Lateral Crystallization (MILC) method. This Nickel silicide acts as a defect center, and this defect is one of the biggest reason of the high leakage current. In this research, we fabricated polycrystalline TFTs with novel method called Edge Cut (EC). With this new fabrication method, we assumed that nickel silicide at the edge of the channel region is reduced. Electrical properties are measured and trap state density also calculated using Levinson & Proano method.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.153-156
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• 2004

A newly developed flexible active-matrix (AM-) electrophoretic display (EPD) is reported. The AM-EPD features: (1) low-temperature polycrystalline silicon (LTPS) thin film transistor (TFT) technology, (2) fully integrated scan- and data-drivers, (3) flexibility and light-weight realized by transferring the whole circuits onto a plastic substrate using $SUFTLA^{TM}$ (Surface Free Technology by Laser Annealing/Ablation) process. A large storage capacitor is formed in each pixel so that driving electric field can be kept sufficiently strong during a writing period Two-phase driving scheme, a reset-phase which erases a previous image and a writing-phase for writing a new image, was chosen to cope with EPD's high driving voltage. The flexible AM-EPD has been successfully operated with a driving voltage of 8.5 V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.177-177
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• 2009

We examine the process to enhance the productivity of the thin-film transistor-addressed liquid-crystal display (TFT LCD) panels with the objective of optimizing the relation between the Type of color PR dispense nozzle and the amount of dispensing of color PR consumption, directly affecting a spectroscopic analysis. Most manufacturers of the panels have been utilizing a spin-type coater. We show that we successfully optimize the spectral values by controlling the color PR dispense type(Static dispense or Dynamic dispense) and the amount of color PR. From this study, we accomplished to decrease 43% in color PR consumption and to decrease 30% in color PR Stained, to decrease 30% rework rate.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1422-1423
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• 2011

Passivation 막이 증착될 때 산화물 반도체의 백 인터페이스에 주는 플라즈마 데미지와 화학적으로 유도된 데미지를 최소화하기 위하여 산화물 반도체의 보호막으로서 자가조립단분자막(SAM) 적용을 제안한다. TFT가 PECVD나 용액을 기반으로 한 재료로 passivation 될 때 산화물 반도체의 back interface는 플라즈마 데미지와 화학적으로 유도되는 데미지를 피할 수 없다. 자가조립단분자막을 적용함으로써 플라즈마 데미지를 막아줌으로써 이동도와 문턱전압 이하에서의 기울기(SS)의 열화와 용액을 기반으로 한 passivation으로 인한 특성변화(Von)를 최소화 하였다.

• Journal of Information Display
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• v.12 no.3
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• pp.121-124
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• 2011

The mechanism for lattice-shaped mura defects was proposed by characterizing the electro-optic properties of liquid crystal (LC), which showed different transmission properties between the normal and mura defect areas. An increase in the mura defect rate was observed when the dotted LC in the one drop filling (ODF) was exposed for a longer time. The dotted LC droplet at the edge evaporated more rapidly than that in the center. This resulted in a higher concentration of polar singles at the edge of the dotted LC droplet, leading to a higher ${\Delta}n$ value and higher transmittance. This implies that the reductio of the exposure time of the dotted LC to air plays a critical role in decreasing the occurrence of lattice-shaped mura defects in ODF.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1081-1084
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• 2007

System on Panel (SOP) can integrate many functions by Thin Film Transistor (TFT) circuits on an insulator substrate without using external driver LSIs. However, to make practical SOP has become more and more difficult because of rapid cost reduction of the driver LSIs. This paper will review the circuit design technology trend for SOP and introduce an example of a practical SOP, 2.0inch QVGA full color active matrix OLED with 8bit source driver.

• Macromolecular Research
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• v.10 no.2
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• pp.75-79
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• 2002

Organic materials have considerable attention as active semiconductors for device applications such as thin-film transistors (TFTs) and diodes. Pentacene is a p-type organic semiconducting material investigated for TFTs. In this paper, we reported the morphological and electrical characteristics of pentacene TFT films. The pentacene transistors showed the mobility of 0.8 $\textrm{cm}^2$/Vs and the grains larger than 1 ${\mu}{\textrm}{m}$. Deep-level transient spectroscopy (DLTS) measurements were carried out on metal/insulator/organic semiconductor structure devices that had a depletion region at the insulator/organic-semiconductor interface. The duration of the capacitance transient in DLTS signals was several ten of seconds in the pentacene, which was longer than that of inorganic semiconductors such as Si. Based on the DLTS characteristics, the energy levels of hole and electron traps for the pentacene films were approximately 0.24, 1.08, and 0.31 eV above Ev, and 0.69 eV below Ec.