• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Progress in Superconductivity
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• 제12권2호
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• pp.118-123
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• 2011

The properties of $2^{nd}$ generation high temperature superconducting wire, coated conductor strongly depend on the quality of superconducting oxide layer and property of metal substrate is one of the most important factors affecting the quality of coated conductor. Good mechanical and chemical stability at high temperature are required to maintain the initial integrity during the various process steps required to deposit several layers consisting coated conductor. And substrate need to be nonmagnetic to reduce magnetization loss for ac application. Hastelloy and stainless steel are the most suitable alloys for metal substrate. One of the obstacles in using stainless steel as substrate for coated conductor is its difficulties in making smooth surface inevitable for depositing good IBAD layer. Conventional method involves several steps such as electro polishing, deposition of $Al_2O_3$ and $Y_2O_3$ before IBAD process. Chemical solution deposition method can simplify those steps into one step process having uniformity in large area. In this research, we tried to improve the surface roughness of stainless steel(SUS310). The precursor coating solution was synthesized by using yttrium complex. The viscosity of coating solution and heat treatment condition were optimized for smooth surface. A smooth amorphous $Y_2O_3$ thin film suitable for IBAD process was coated on SUS310 tape. The surface roughness was improved from 40nm to 1.8 nm by 4 coatings. The IBAD-MgO layer deposited on prepared substrate showed good in plane alignment(${\Delta}{\phi}$) of $6.2^{\circ}$.

• 한국결정성장학회지
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• 제20권3호
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• pp.107-112
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• 2010

높은 광흡수 계수를$(1{\times}10^5cm^{-1})$ 가지는 CIGS는 Ga의 비율에 따라서 밴드갭을 조절할 수 있다는 장점을 지니고 있다. CIGS의 밴드갭은 Ga의 비율에 따라 $CuInSe_2$(Eg: 1.0 eV)에서 $CuGaSe_2$(Eg: 1.68 eV)까지의 범위에 존재하며, 태양전지에 서 이상적인 fill factor 모양을 가지도록 Ga의 비율을 높게 조성한다. CIGS 흡수층을 제작하는 방법에는 co-evaporator 방식이 가장 널리 사용되며 연구되고 있다. 이에 본 연구에서는 수평 형태의 hydride vapor transport (HVT)법을 고안하여 CIGS 나노 구조 및 에피성장을 시도하였다. HVT법은 $N_2$ 분위기에서 원료부의 CIGS 혼합물을 HCl과 반응시켜 염화물 기체상태로 변환 후 growth zone까지 이동하여 성장을 하는 방식이다. 성장기판은 c-$Al_2O_3$ 기판과 u-GaN을 사용하였다. 성장 후 field emission scanning electron microscopy(FE-SEM)과 energy dispersive spectrometer(EDS)를 이용하여 관찰하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.66-66
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• 2008

Most of the properties of ITO films depend on their substrate nature, deposition techniques and ITO film composition. For the display panel application, it is normally deposited on the glass substrate which has high strain point (>575 degree) and must be deposited at a temperature higher than $250^{\circ}C$ and then annealed at a temperature higher than $300^{\circ}C$ in order to high optical transmittance in the visible region, low reactivity and chemical duration. But the high strain point glass (HSPG) used as FPDs is blocking popularization of large sizes FPDs because it is more expensive than a soda lime glass (SLG). If the SLG could be used as substrate for FPDs, then diffusion of Na ion from the substrate occurs into the ITO films during annealing or heat treatment on manufacturing process and it affects the properties. Therefore proper care should be followed to minimize Na ion diffusion. In this study, we investigate the electrical, optical and structural properties of ITO films deposited on the SLG and the Asahi glass(PD200) substrate by rf magnetron sputtering using a ceramic target ($In_2O_3:SnO_2$, 90:10wt.%). These films were annealed in $N_2$ and air atmosphere at $400^{\circ}C$ for 20min, 1hr, and 2hrs. ITO films deposited on the SLG show a high electrical resistivity and structural defect as compared with those deposited on the PD200 due to the Na ion from the SLG on diffuse to the ITO film by annealing. However these properties can be improved by introducing a barrier layer of $SiO_2$ or $Al_2O_3$ between ITO film and the SLG substrate. The characteristics of films were examined by the 4-point probe, FE-SEM, UV-VIS spectrometer, and X-ray diffraction. SIMS analysis confirmed that barrier layer inhibited Na ion diffusion from the SLG.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.214-217
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• 1999

We investigated the quench characteristics of meander line type resistive superconducting fault current limiters based on YBCO thin films grown on 2" diameter LaAlO$_3$ substrates. A gold layer was deposited onto the 0.4 ${\mu}$ m thick YBCO film to disperse the heat generated at hot spots, prior to patterning into 1 mm wide meander lines by photolithography. The limiters were tested with simulated fault currents of various amplitudes. The quench started at 10 A and was completed within 1 msec at the fault current of 65 A$_{peak}$. The dynamic quench characteristics were explained based on the heat conduction within the film and the heat transfer between the film and the surrounding liquid nitrogen. The heat transfer coefficient per unit area was estimated to be 3.0 W/cm$^2$K.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.77.1-77.1
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• 2013

Atomic layer deposition (ALD) is known for its self-limiting reaction, which offers atomic-level controllability of the growth of thin films for a wide range of applications. The self-limiting mechanism leads to very useful properties, such as excellent uniformity over a large area and superior conformality on complex structures. These unique features of ALD provide promising opportunities for future electronics. Although the ALD of Al2O3 film (using trimethyl-aluminum and water as a metal precursor and oxygen source, respectively) can be regarded as a representative example of an ideal ALD based on the completely self-limiting reaction, there are many cases deviating from the ideal ALD reaction in recently developed ALD processes. The nonconventional aspects of the ALD reactions may strongly influence the various properties of the functional materials grown by ALD, and the lack of comprehension of these aspects has made ALD difficult to control. In this respect, several dominant factors that complicate ALD reactions, including the types of metal precursors, non-metal precursors (oxygen sources or reducing agents), and substrates, will be discussed in this presentation. Several functional materials for future electronics, such as higher-k dielectrics (TiO2, SrTiO3) for DRAM application, and resistive switching materials (NiO) for RRAM application, will be addressed in this talk. Unwanted supply of oxygen atoms from the substrate or other component oxide to the incoming precursors during the precursor pulse step, and outward diffusion of substrate atoms to the growing film surface even during the steady-state growth influenced the growth, crystal structure, and properties of the various films.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.287.1-287.1
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• 2016

Three-dimensional (3-D) semiconductor nanoarchitectures, including nano- and micro- rods, pyramids, and disks, are emerging as one of the most promising elements for future optoelectronic devices. Since these 3-D semiconductor nanoarchitectures have many interesting unconventional properties, including the use of large light-emitting surface area and semipolar/nonpolar nano- or micro-facets, numerous studies reported on novel device applications of these 3-D nanoarchitectures. In particular, 3-D nanoarchitecture devices can have noticeably different current spreading characteristics compared with conventional thin film devices, due to their elaborate 3-D geometry. Utilizing this feature in a highly controlled manner, color-tunable light-emitting diodes (LEDs) were demonstrated by controlling the spatial distribution of current density over the multifaceted GaN LEDs. Meanwhile, for the fabrication of high brightness, single color emitting LEDs or laser diodes, uniform and high density of electrical current must be injected into the entire active layers of the nanoarchitecture devices. Here, we report on a new device structure to inject uniform and high density of electrical current through the 3-D semiconductor nanoarchitecture LEDs using metal core inside microtube LEDs. In this work, we report the fabrications and characteristics of metal-cored coaxial $GaN/In_xGa_{1-x}N$ microtube LEDs. For the fabrication of metal-cored microtube LEDs, $GaN/In_xGa_{1-x}N/ZnO$ coaxial microtube LED arrays grown on an n-GaN/c-Al2O3 substrate were lifted-off from the substrate by wet chemical etching of sacrificial ZnO microtubes and $SiO_2$ layer. The chemically lifted-off layer of LEDs were then stamped upside down on another supporting substrates. Subsequently, Ti/Au and indium tin oxide were deposited on the inner shells of microtubes, forming n-type electrodes of the metal-cored LEDs. The device characteristics were investigated measuring electroluminescence and current-voltage characteristic curves and analyzed by computational modeling of current spreading characteristics.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.115-115
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• 1999

GaN는 직접천이형 wide band gap(3.4eV) 반도체로서 청색/자외선 발광소자 및 고출력 전자장비등에의 응용성 때문에 폭넓게 연구되고 있다. 이러한 넓은 분야의 응용을 위해서는 열 적으로 안정된 Ohmic contact을 반드시 실현되어야 한다. n-type GaN의 경우에는 GaN계면에서의 N vacancy가 n-type carrier로 작용하기 때문에 Ti, Al, 같은 금속을 접합하여 nitride를 형성함에 의해서 낮은 접촉저항을 갖는 Ohmic contact을 하기가 쉽다. 그러나 p-type의 경우에는 일 함수가 크고 n-type와 다르게 nitride가 형성되지 않는 금속이 Ohmic contact을 할 가능성이 많다. 시료는 HF(HF:H2O=1:1)에서 10분간 초음파 세척을 한 후 깨끗한 물에 충분히 헹구었다. 그런 후에 고순도 Ar 가스로 건조시켰다. Pd와 Ni은 열적 증착법(thermal evaporation)을 사용하여 p-GaN에 상온에서 증착하였다. 현 연구에서는 열처리에 의한 Pd의 clustering을 줄이기 위해서 wetting이 좋은 Ni을 Pd 증착 전과 후에 삽입하였으며, monchromatic XPS(x-ray photoelectron spectroscopy) 와 SAM(scanning Auger microscopy)을 사용하여 열처리 전과 40$0^{\circ}C$, 52$0^{\circ}C$ 그리고 695$0^{\circ}C$에서 3분간 열처리 후의 온도에 따른 morphology 변화, 계면반응(interfacial reaction) 및 벤드 휨(band bending)을 비교 연구하였다. Nls core level peak를 사용한 band bending에서 Schottky barrier height는 Pd/Ni bi-layer 접합시 2.1eV를, Ni/Pd bi-layer의 경우에 2.01eV를 얻었으며, 이는 Pd와 Ni의 이상적인 Schottky barrier height 값 2.38eV, 2.35eV와 비교해 볼 때 매우 유사한 값임을 알 수 있다. 시료를 후열처리함에 의해 52$0^{\circ}C$까지는 barrier height는 큰 변화가 없으나, $650^{\circ}C$에서 3분 열처리 후에 0.36eV, 0.28eV 만큼 band가 더 ？을 알 수 있었다. Pd/Ni 및 Ni/Pd 접합시 $650^{\circ}C$까지 후 열 처리 과정에서 계면에서 matallic Ga은 온도에 비례하여 많은 양이 형성되어 표면으로 편석(segregation)되어지나, In-situ SAM을 이용한 depth profile을 통해서 Ni/Pd, Pd/Ni는 증착시 uniform하게 성장함을 알 수 있었으며, 후열처리 함에 의해서 점차적으로 morphology 의 변화가 일어나기 시작함을 볼 수 있었다. 이는 $650^{\circ}C$에서 열처리 한후의 ex-situ AFM을 통해서 재확인 할 수 있었다. 이상의 결과로부터 GaN에 Pd를 접합 시 심한 clustering이 형성되어 Ohoic contact에 문제가 있으나 Pd/Ni 혹은 Ni/Pd bi-layer를 사용함에 의해서 clustering의 크기를 줄일 수 있었다. Clustering의 크기는 Ni/Pd bi-layer의 경우가 작았으며, $650^{\circ}C$ 열처리 후에 barrier height는 Pd/Ni bi-layer의 경우에도 Ni의 영향을 받음을 알 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• 한국광학회지
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• 제18권6호
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• pp.452-460
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• 2007

ZERODUR와 용융 석영으로 저산란 반사경을 제작하고 산란 특성을 연구하였다. Bowl feed 법을 이용하여 초연마면인 표면거칠기 0.326 ${\AA}$인 용융 석영 기판과 표면거칠기 0.292 ${\AA}$의 ZERODUR 기판을 얻었다. 이온빔 스퍼터링 방법으로 초연마된 기판 위에 $SiO_2$와 $Ta_2O_5$를 교번으로 22층을 증착하여 다층박막 고반사 거울을 얻었다. 용융 석영 반사경과 ZERODUR 반사경의 산란이 각각 4.6 ppm과 30.9 ppm으로 측정되었으며, 이로부터 산란이 매우 작은 경우 기판의 표면거칠기가 산란을 결정하는 주요 파라미터가 아니라는 것을 알았다. 나아가 반사경의 표면거칠기를 AFM으로 측정한 결과. ZERODUR 반사경이 용융 석영 반사경 보다 박막의 표면거칠기가 2.3배 더 높게 측정 되었다. 이 결과는 기판-박막 경계면에서 박막 형성 초기에 기판의 화학조성 또는 결정방향과 증착물질의 상호관계로 인하여 박막 형성 초기에 표면거칠기가 급격히 나빠져서 발생하는 것으로 유추되었다. SEO 300A으로 접촉각 측정을 하여 Giriflaco-Good-Fowkees-Young 방법으로 표면에너지를 계산하였다. 표면거칠기 0.46 ${\AA}$을 갖는 용융 석영 기판이 표면거칠기 0.31 ${\AA}$을 갖는 ZERODUR 기판보다 접촉각이 더 작고 표면에너지는 크게 나타났다. 이러한 차이가 기판 종류에 따라 박막형성 초기에 표면거칠기를 다르게 하는 한 요인으로 판단되며, 기판의 표면에너지가 높을수록 미려한 박막표면을 얻는 것으로 확인되었다. ZERODUR의 표면에너지 차이를 설명하기 위해 XPS 분석으로 용융 석영은 Si, O로 구성되었고 ZERODUR는 Si, O, Al, Na 그리고 F로 구성되었다는 것을 알 수 있었다.