• 제목/요약/키워드: thermal vapor deposition

검색결과 539건 처리시간 0.024초

저온 Si계 에피 성장기술에서 실험계획법에 의한 in-situ H$_2$ bake 및 GeH$_4$ clean 공정 최적화 (The process optimization of in-situ H$_2$ bake and GeH$_4$ clean in low temperature Si epitaxy using design of experiment)

  • 이경수
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 추계학술대회 논문집
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    • pp.54-58
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    • 1994
  • H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

탑 게이트 탄소나노튜브 트랜지스터 특성 연구 (Properties of CNT field effect transistors using top gate electrodes)

  • 박용욱;윤석진
    • 센서학회지
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    • 제16권4호
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    • pp.313-318
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    • 2007
  • Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

다중 코팅된 $Si_3N_4-TiC$ 세라믹의 특성 (Characteristics of Multilayer Coated $Si_3N_4-TiC$ Ceramic)

  • 김동원;천성순
    • 한국재료학회지
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    • 제1권1호
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    • pp.9-17
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    • 1991
  • 화학증착법에 의해 $Si_3N_4-TiC$ 복합재료 위에 코팅된 TiC 박막은 TiN 박막에 비하여 우수한 미세구조와 열충격저항, 계면결합을 가지고 있는 것으로 나타났다. 화학증착법에 의한 TiN 박막은 TiC 박막에 비해 강철과의 마찰계수가 작고 화학적으로 안정하였다. 실험결과는 코팅된 절삭공구가 우수한 내 마모성을 갖고 있는 것으로 나타났다. 또한, 다중 코팅된 절삭공구는 단일 코팅된 공구보다 우수한 내 마모성을 보였다

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진공증착중합법에 의해 제조된 6FDA/DDE 폴리이미드박막의 열처리에 따른 특성에 관한 연구 (A study on the curing characteristics of polyimide thin film fabricated by vapor deposition polymerization)

  • 이봉주;김형권;진윤영;박구범;김영봉;이덕출
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1997년도 하계학술대회 논문집 C
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    • pp.1552-1554
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    • 1997
  • In this paper, thin films of PI were fabricated VDPM of dry processes which are easy to control the film's thickness and hard to pollute due to volatile solvents. From FT-IR, PAA thin films fabricated by VDP were changed to PI thin films by thermal curing. From AFM and ellipsometer experimental, the higher curing temperature is, the films thickness decreases and reflectance increases. Therefore, PI could be fabricated stable by increasing curing temperature.

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집합조직이 존재하는 TiN 코팅 층의 마찰, 마멸, 내부식 특성에 관한 연구 (Study on the Frictional Behavior, Wear and Corrosion Resistance of Textured TiN Coated Layers)

  • 김희동;김인수;성동영;이민구
    • 소성∙가공
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    • 제12권4호
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    • pp.394-400
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    • 2003
  • TiN coated films exhibit excellent mechanical properties such as high wear, erosion and corrosion resistances and a high thermal stability. Therefore, they are widely applied to a coating material in tools, ornaments, parts and semiconductors. However, the fracture of TiN coated films frequently occurs. The distribution of preferred orientations, i.e., texture, of TiN coated films strongly influences the fracture behavior of these films. In the present study. various TiN coating layers having different textures were prepared by the reactive ion physical vapor deposition and the texture dependence of friction coefficient, erosion and corrosion in these coating layers was investigated. The sample depicting the (115) texture parallel to the coating layer normal displayed a flatter surface than that observed from the sample having the (111) texture. The friction coefficient of TiN thin films was hardly dependent on the texture of coated samples. The samples having (115) texture displayed higher wear, erosion and corrosion resistances than the samples having (111) texture.

증착중합법에 의한 폴리이미드 박막의 작성에 관한 연구 (A study on the fabrication of PI thin films by VDP method)

  • 김형권;한상옥;김진식;박광현;진경시;이덕출
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 C
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    • pp.1394-1396
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    • 1994
  • Polyimide thin films were fabricated an using vapor deposition polymerization apportus, and their FT-IR and TGA characteristics were investigated. The peaks of $720cm^{-1}$ and $1380cm^{-1}$ show C=O stretch mode and C-N stretch mode, and that of the cured polyimide at $350^{\circ}C$ were sturated. $T_d$(Depolymerization temperature) was showed at $405^{\circ}C$ from research of thermal resistivity characteristics by TGA It was possible to fabrication of polyimide thin film by VDPM.

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씨앗층과 급속 열처리가 화학 기상 증착법에 의한(Ba, Sr)TiO3 박막의 특성에 미치는 영향 (Effects of Seed Layer and Rapid Thermal Annealing on the Properties of (Ba, Sr)TiO3 Films Prepared by Chemical vapor deposition)

  • 최영철
    • 마이크로전자및패키징학회지
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    • 제4권2호
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    • pp.47-54
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    • 1997
  • Pt/SiO2/Si을 기판으로 사용하고 RF 마그네트론 스퍼터링에 의한 (Ba, Sr)TiO3 (BST) 씨앗층을 약 10nm 정도의 두께로 입힌 다음 그 상부에 화학 기상증착법으로 BST를 증착하여 BST seed layer가 CVD BST 박막의 특성에 미치는 영향을 조사하였다. 또한 급 속열처리가 BST 박막과 커패시터의 특성에 미치는 영향도 조사하였다. Seed layer와 급속 열처리에 의해 박막의 결정성이 향상되었으며 이로인해 유전상수가 증가되었고 주파수에 대 한 유전특성도 개선되었다. Seed layer를 도입함으로써 BST 박막과 Pt 하부전극 사이의 계 면에 존재하고 있는 산소부족\ulcorner이 사라짐을 확인할수 있었으며 이로 인해 Pt/BST/Pt 커\ulcorner 시터의 누설전류가 감소하였다. 또한 급속 열처리에 의해 BST/Pt 계면에서 트랩된 전자의 농도가 감소함으로써 누설전류 특성이 개선됨을 알수 있었다. Seed layer 위에 증착된 CVD BST 박막의 유전상수는 증착온도가 증가함에 따라 증가하였으나 누설전류도 같이 증가하 였다.

Bonding and Etchback Silicon-on-Diamond Technology

  • Jin, Zengsun;Gu, Changzhi;Meng, Qiang;Lu, Xiangyi;Zou, Guangtian;Lu, Jianxial;Yao, Da;Su, Xiudi;Xu, Zhongde
    • The Korean Journal of Ceramics
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    • 제3권1호
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    • pp.18-20
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    • 1997
  • The fabrication process of silicon-diamond(SOD) structure wafer were studied. Microwave plasma chemical vapor deposition (MWPCVD) and annealing technology were used to synthesize diamond film with high resistivity and thermal conductivity. Bonding and etchback silicon-on-diamond (BESOD) were utilized to form supporting substrate and single silicon thin layer of SOD wafer. At last, a SOD structure wafer with 0.3~1$\mu\textrm{m}$ silicon film and 2$\mu\textrm{m}$ diamond film was prepared. The characteristics of radiation for a CMOS integrated circuit (IC) fabricated by SOD wafer were studied.

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암모니아 식각 가스 도입에 의한 고순도 탄소나노튜브의 합성 (Carbon Nanotube Synthesis with High Purity by Introducing of NH3 Etching Gas)

  • 이선우;이붕주
    • 전기학회논문지
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    • 제62권6호
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    • pp.782-785
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    • 2013
  • Multi-walled carbon nanotubes were synthesized on Ni catalyst using thermal chemical vapor deposition. By introducing ammonia gas during the CNT synthesis process, clean and vertically aligned CNTs without impurities could be prepared. As the ammonia gas increased a partial pressure of hydrogen in the mixed gas during the CNT synthesis process, we could control the CNT synthesis rate appropriately. As the ammonia gas has an etching ability, amorphous carbon species covering the catalyst particles were effectively removed. Therefore catalyst particles could maintain their catalytic state actively during the synthesis process. Finally, we could obtain clean and vertically aligned CNTs by introducing $NH_3$ gas during the CNT synthesis process.

집적화된 3 극형 탄소 나노 튜브 전자 방출원의 제작 (Fabrication of Integrated Triode-type CNT Field Emitters)

  • 이정아;문승일;이윤희;주병권
    • 한국전기전자재료학회논문지
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    • 제17권2호
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    • pp.212-216
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    • 2004
  • In this paper, we have fabricated a triode field emitter using carbon nanotubes (CNTs) directly grown by thermal chemical vapor deposition(CVD) method as an electron omission source. Vertically aligned CNTs have been grown in the center of the gate hole, to the size of 1.5 ${\mu}{\textrm}{m}$ in diameter, with help of a sacrificial layer of a type generally used in metal tip process. By the method of tilling the substrate, we made CNTs emitters both with and without SiO$_2$layer, a sidewall protector, deposited on sidewall of gate. After that we researched the electrical characteristics about two types of emitters. In effect, a sidewall protector can enhance the electrical characteristics by suppressing the problem of short circuits between the gate and the CNTs. The leakage current of an emitter with a sidewall protector is approximately sevenfold lower than that of an emitter without it at a gate voltage of 100 V.