• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.86-93
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• 2004

The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation Sharing Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.773-778
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• 1993

A new approach is proposed for the DCT which is widely utilized in the image processing, The approach replaces mutiplications with shift and additions, In the image restored by the proposed DCT and IDCT, no visible degration is observed and PSNR(Peak to Peak Signal to Noise Ratio) is greater than 35 dB for all cases, proving the usefulness of the proposal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.47-56
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• 1993

In this paper, pyramidal VQ image coding by DCT classifier based on HVS is studied. The proposed DCT classifier based on HVS is that the transform subblocks of the image are mlultiplied by MTF which is a sort of band pass filter and sorted by the magnitude of their ac energy levels and classifeid into three classes such as low, middle and high variance class by the threshold and then edges are detected in comparison of the energy sum of ac transform coefficients corresponding to the different edge directions.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2019.11a
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• pp.246-248
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• 2019

In the ongoing standardization of Versatile Video Coding (VVC), DCT-2, DST-7 and DCT-8 are accounted as the vital transform kernels. While storing all of those transform kernels, ROM memory storage is considered as the major problem. So, to deal with this scenario, a common sparse unified matrix concept is introduced in this paper. From the proposed matrix, any point transform kernels (DCT-2, DST-7, DCT-8, DST-4 and DCT-4) can be achieved after some mathematical computation. DCT-2, DST-7 and DCT-8 are the used major transform kernel in this paper.

• Journal of the Korea Society of Computer and Information
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• v.16 no.4
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• pp.61-71
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• 2011

In this paper, we proposed the method for detecting text region on image using DCT-coefficient and transition-map analysis. The detecting rate of traditional method for detecting text region using DCT-coefficient analysis is high, but false positive detecting rate also is high and the method using transition-map often reject true text region in step of verification because of sticky threshold. To overcome these problems, we generated PTRmap(Promising Text Region map) through DCT-coefficient analysis and applied PTRmap to method for detecting text region using transition map. As the result, the false positive detecting rate decreased as compared with the method using DCT-coefficient analysis, and the detecting rate increased as compared with the method using transition map.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.1 no.3
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• pp.97-103
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• 2008

In this paper, $256{\times}256$ input image is classified into a validity block and an edge block of $8{\times}8$ block for image compression. DCT(Discrete Cosine Transform) is executed only for the DC coefficient that is validity coefficients for a validity block. Predict the position where a quantization coefficient becomes 0 for an edge block, I propose new algorithm to execute DCT in the reduced region. Not only this algorithm that I proposed reduces computational complexity of FDCT(Forward DCT) and IDCT(Inverse DCT) and decreases encoding time and decoding time. I let compressibility increase by accomplishing other stability verticality zigzag scan by the block size that was classified for each block at the time of huffman encoding each. In addition, the algorithm that I suggested reduces Run-Length by accomplishing the level verticality zigzag scan that is good for a classified block characteristic and, I offer the compressibility that improved thereby.

• Journal of the Korea Computer Industry Society
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• v.4 no.4
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• pp.433-442
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• 2003

The performance of communication systems should be tested against a set of requirements. To this end, noise generation systems are used to generate noise signals with specified characteristics. In recent study, noise generation system using DCT outperforms the conventional noise generation system when a noise model requires complicated PSD(Power Spectral Density) specifications. In this paper low area/power structures of non-DCT block in DCT-based noise generation system are proposed. Simulation results show that the low area structure results in area reduction by 61-64% and the low power structure achieves power reduction by 88-89% except DCT blocks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6C
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• pp.594-599
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• 2007

In this paper, we present new representation of DCT/DFT matrices via one hybrid architecture. Based on a element inverse matrix factorization algorithm, we show that the DCT and DFT have a same recursive computational pattern, and we can develop an hybrid architecture by using some diagonal matrices.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.175-178
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• 2003

This paper proposes a stereo image insertion technique on DCT coefficients using the embedded method developed in the digital watermarking in due consideration of compatibility with conventional 2D system such JPEG, and MPEG. In conventional transmission method users with conventional digital TV cannot watch the transmitted 3D image sequence as 2D image, because of affectivity of conventional 3D image compression. To give an answer, in this paper, DCT coefficients are changed according to its disparity on YCbCr channels. Our method can insert stereo images into a conventional image compression method based on DCT.